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december 1997 1/84 this is preliminary information on a new product in development or undergoing evaluation. details are subject to change without notice. r rev. 2.2 st6365, st6375, st6385 ST6367, st6377, st6387 8-bit mcus with on-screen-display for tv tuning n 4.5 to 6v supply operating range n 8mhz maximum clock frequency n user program rom: up to 20140 bytes n reserved test rom: up to 340 bytes n data rom: user selectable size n data ram: 256 bytes n data eeprom: 384 bytes n 42-pin shrink dual in line plastic package n up to 22 software programmable general purpose inputs/outputs, including 2 direct led driving outputs n two timers each including an 8-bit counter with a 7-bit programmable prescaler n digital watchdog function n serial peripheral interface (spi) supporting s- bus/ i 2 c bus and standard serial protocols n spi for external frequency synthesis tuning n 14 bit counter for voltage synthesis tuning n up to six 6-bit pwm d/a converters n afc a/d converter with 0.5v resolution n five interrupt vectors (irin/nmi, timer 1 & 2, vsync, pwr int.) n on-chip clock oscillator n 5 lines by 15 characters on-screen display generator with 128 characters n all rom types are supported by pin-to-pin eprom and otp versions. n the development tool of the st6365, st6375, st6385, ST6367, st6377, st6387 microcon- trollers consists of the st638x-emu2 emula- tion and development system to be connected via a standard rs232 serial line to an ms-dos personal computer. device summary device rom (bytes) d/a converter st6365 8k 4 ST6367 8k 6 st6375 14k 4 st6377 14k 6 st6385 20k 4 st6387 20k 6 psdip42 (refer to end of document for ordering information) 1
2/84 table of contents 84 1 st6365, st6375, st6385, ST6367, st6377, st6387 . . . . . . . . 1 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3 memory spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.1 stack space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.2 program space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.3 data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3.4 data ram/eeprom/osd ram addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 clocks, reset, interrupts and power saving modes . . . . . . . . . . . . . . . . . . . . . 18 3.1 on-chip clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.1 reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 3.2.2 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.3 watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2.4 application note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 3.2.5 mcu initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3 hardware activated digital watchdog function . . . . . . . . . . . . . . . . . . . . 21 3.4 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.4.1 interrupt vectors/sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.4.2 interrupt priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.4.3 interrupt option register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.4.4 interrupt procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.4.5 st638x interrupt details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.5 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 3.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.5.3 exit from wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.1 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.1.1 details of i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 4.1.2 i/o pin programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.1.3 input/output configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.1.4 i/o port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.2 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.2.1 timer operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.2.2 timer status control registers (tscr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.2.3 timer counter registers (tcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.2.4 timer prescaler registers (pscr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3/84 table of contents 1 4.3 serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.3.1 s-bus/i 2 c bus protocol information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.3.2 s-bus/i 2 c bus timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.3.3 compatibility s-bus/i 2 c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.3.4 std spi protocol (shift register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.3.5 spi data/control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.4 14-bit voltage synthesis tuning peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.4.1 output details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.4.2 vs tuning cell registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.5 6-bit pwm d/a converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.6 afc a/d comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.6.1 a/d comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.7 dedicated latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.8 on-screen display (osd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.8.1 format specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5 software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.1 st6 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.2 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.3 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.3 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.4 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7 general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.2 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.3 customer eeprom initial contents: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.4 osd test character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.5 ordering information table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4/84 st6365, st6375, st6385 ST6367, st6377, st6387 st63e85, t85, st63e87, t87 . . . . . . . . . . . . . . . . . . . . . . . . . . 71 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 1.3 eprom/otp description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 1.4 power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 1.5 eprom erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 2.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 2.3 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 2.4 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3 general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 3.1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 3.2 customer eeprom initial contents: format . . . . . . . . . . . . . . . . . . . . . . . . . . 81 3.3 osd test character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 3.4 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.5 ordering information table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5/84 st6365, st6375, st6385 ST6367, st6377, st6387 1 general description 1.1 introduction the st6365,67,75,77,85,87 microcontrollers are members of the 8-bit hcmos st638x family, a series of devices specially oriented to tv applica- tions. different rom size and peripheral configu- rations are available to give the maximum applica- tion and cost flexibility. all st638x members are based on a building block approach: a common core is surrounded by a combination of on-chip pe- ripherals (macrocells) available from a standard li- brary. these peripherals are designed with the same core technology providing full compatibility and short design time. many of these macrocells are specially dedicated to tv applications. the macrocells of the st638x family are: two timer peripherals each including an 8-bit counter with a 7-bit software programmable prescaler (timer), a digital hardware activated watchdog function (dh- wd), a 14-bit voltage synthesis tuning peripheral, a serial peripheral interface (spi), up to six 6-bit pwm d/a converters, an afc a/d converter with 0.5v resolution, an on-screen display (osd) with 15 characters per line and 128 characters (in two banks each of 64 characters). in addition the fol- lowing memory resources are available: program rom (up to 20k), data ram (256 bytes), eep- rom (384 bytes). refer to pin configurations fig- ures and to st638x device summary ( table 1 ) for the definition of st638x family members and a summary of differences among the different types. table 1. device summary device rom (bytes) ram (bytes) eeprom (bytes) afc vs d/a colour pins eprom devices st6365 8k 256 384 yes yes 4 3 st63e85 ST6367 8k 256 384 yes yes 6 3 st63e87 st6375 14k 256 384 yes yes 4 3 st63e85 st6377 14k 256 384 yes yes 6 3 st63e87 st6385 20k 256 384 yes yes 4 3 st63e85 st6387 20k 256 384 yes yes 6 3 st63e87
6/84 st6365, st6375, st6385 ST6367, st6377, st6387 figure 1. block diagram test irin/pc6 interrupt up to 20kbytes pc stack level 1 stack level 2 stack level 3 stack level 4 stack level 5 stack level 6 power supply oscillator reset data rom user selectable data ram 256 bytes port a port b port c 8 bit core test timer 1 pa0 - pa7* v dd v ss oscin oscout reset user program memory timer 2 inputs data eeprom 384 bytes pc2, pc4 - pc7* d/a outputs afc & vs* r, g, b, blank vs output & on-screen digital watchdog da0 - da5 *refer to pin description for additional information serial peripheral pc0/scl pc1/sda pc3/sen timer afc outputs display interface hsync, vsync vr01753 osdoscout osdoscin pb0 - pb2, pb4 pb6*
7/84 st6365, st6375, st6385 ST6367, st6377, st6387 1.2 pin description v dd and v ss . power is supplied to the mcu using these two pins. v dd is power and v ss is the ground connection. oscin, oscout. these pins are internally con- nected to the on-chip oscillator circuit. a quartz crystal or a ceramic resonator can be connected between these two pins in order to allow the cor- rect operation of the mcu with various stability/ cost trade-offs. the oscin pin is the input pin, the oscout pin is the output pin. reset . the active low reset pin is used to start the microcontroller to the beginning of its program. additionally the quartz crystal oscillator will be dis- abled when the reset pin is low to reduce power consumption during reset phase. test . the test pin must be held at v ss for nor- mal operation. pa0-pa7 . these 8 lines are organized as one i/o port (a). each line may be configured as either an input with or without pull-up resistor or as an out- put under software control of the data direction register. pins pa4 to pa7 are configured as open- drain outputs (12v drive). on pa4-pa7 pins the in- put pull-up option is not available while pa6 and pa7 have additional current driving capability (25ma, v ol :1v). pa0 to pa3 pins are configured as push-pull. pb0-pb2, pb4-pb6 . these 6 lines are organized as one i/o port (b). each line may be configured as either an input with or without internal pull-up resistor or as an output under software control of the data direction register. pc0-pc7 . these 8 lines are organized as one i/o port (c). each line may be configured as either an input with or without internal pull-up resistor or as an output under software control of the data direc- tion register. pins pc0 to pc3 are configured as open-drain (5v drive) in output mode while pc4 to pc7 are open-drain with 12v drive and the input pull-up options does not exist on these four pins. pc0, pc1 and pc3 lines when in output mode are anded with the spi control signals and are all open-drain. pc0 is connected to the spi clock sig- nal (scl), pc1 with the spi data signal (sda) while pc3 is connected with spi enable signal (sen, used in s-bus protocol). pin pc4 and pc6 can also be inputs to software programmable edge sensitive latches which can generate interrupts; pc4 can be connected to power interrupt while pc6 can be connected to the irin/nmi interrupt line. da0-da5 . these pins are the six pwm d/a out- puts of the 6-bit on-chip d/a converters. these lines have open-drain outputs with 12v drive. the output repetition rate is 31.25khz (with 8mhz clock). afc . this is the input of the on-chip 10 levels comparator that can be used to implement the afc function. this pin is an high impedance input able to withstand signals with a peak amplitude up to 12v. osdoscin, osdoscout . these are the on screen display oscillator terminals. an oscillation capacitor and coil network have to be connected to provide the right signal to the osd. hsync, vsync . these are the horizontal and vertical synchronization pins. the active polarity of these pins to the osd macrocell can be selected by the user as rom mask option. if the device is specified to have negative logic inputs, then these signals are low the osd oscillator stops. if the de- vice is specified to have positive logic inputs, then when these signals are high the osd oscillator stops. vsync is also connected to the vsync in- terrupt. r, g, b, blank . outputs from the osd. r, g and b are the color outputs while blank is the blank- ing output. all outputs are push-pull. the active polarity of these pins can be selected by the user as rom mask option. vs . this is the output pin of the on-chip 14-bit volt- age synthesis tuning cell (vs). the tuning signal present at this pin gives an approximate resolution of 40khz per step over the uhf band. this line is a push-pull output with standard drive.
8/84 st6365, st6375, st6385 ST6367, st6377, st6387 figure 2. st6365, 75, 85 pin configuration figure 3. ST6367, 77, 87 pin configuration table 2. pin summary 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 vs da1 da2 da3 da4 pb0 pb1 pb2 afc pb4 pb5 pb6 pa0 pa1 pa2 pa3 pa4 pa5 pa6 (hd0) pa7 (hd1) v ss v dd pc0/scl pc1/sda pc2 pc3/sen pc4/pwrin pc5 pc7 oscin oscout test/v pp (1) vsync blank b g r pc6/irin (1) this pin is also the v pp input for otp/eprom devices reset hsync osdoscin osdoscout vr01375 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 da0 da1 da2 da3 da4 da5 pb1 pb2 afc pb4 pb5 pb6 pa0 pa1 pa2 pa3 pa4 pa5 pa6 (hd0) pa7 (hd1) v ss v dd pc0/scl pc1/sda pc2 pc3/sen pc4/pwrin pc5 vs oscin oscout test/v pp (1) vsync blank b g r pc6/irin (1) this pin is also the v pp input for otp/eprom devices reset hsync osdoscin osdoscout vr01375e pin function description da0 to da5 output, open- drain, 12v afc input, high impedance, 12v vs output, push- pull r, g, b, blank output, push- pull hsync, vsync input, pull- up, schmitt trigger osdoscin input, high impedance osdoscout output, push- pull test input, pull- down oscin input, resistive bias, schmitt trigger to reset logic only oscout output, push- pull reset input, pull- up, schmitt trigger input pa0- pa3 i/ o, push- pull, software input pull- up, schmitt trigger input pa4- pa5 i/ o, open- drain, 12v, no input pull- up, schmitt trigger input pa6- pa7 i/ o, open- drain, 12v, no input pull- up, schmitt trigger input, high drive pb0- pb2 i/ o, push- pull, software input pull- up, schmitt trigger input pb4- pb6 i/ o, push- pull, software input pull- up, schmitt trigger input pc0- pc3 i/ o, open- drain, 5v, software input pull- up, schmitt trigger input pc4- pc7 i/ o, open- drain, 12v, no input pull- up, schmitt trigger input v dd , v ss power supply pins
9/84 st6365, st6375, st6385 ST6367, st6377, st6387 1.3 memory spaces the mcu operates in three different memory spaces: stack space, program space and data space. 1.3.1 stack space the stack space consists of six 12 bit registers that are used for stacking subroutine and interrupt re- turn addresses plus the current program counter register. 1.3.2 program space the program space is physically implemented in the rom and includes all the instructions that are to be executed, as well as the data required for the immediate addressing mode instructions, the re- served test area and the user vectors. it is ad- dressed thanks to the 12-bit program counter reg- ister (pc register) and the st6 core can directly address up to 4k bytes of program space. never- theless, the program space can be extended by the addition of 2kbyte memory banks as it is shown in figure 4 , in which the 20k bytes memory is described. these banks are addressed by point- ing to the 000h-7ffh locations of the program space thanks to the program counter, and by writ- ing the appropriate code in the program rom page register (prpr) located at address cah in the data space. because interrupts and common subroutines should be available all the time only the lower 2k byte of the 4k program space are bank switched while the upper 2k byte can be seen as static space. table 3 gives the different codes that allows the selection of the correspond- ing banks. note that, from the memory point of view, the page 1 and the static page represent the same physical memory: it is only a different way of addressing the same location. on the st6385 and st6387, a total of 20480 bytes of rom have been implemented; 20140 bytes are available as user rom while 340 bytes are re- served for testing. figure 4. 20k-byte program space addressing figure 5. memory addressing diagram program counter space 0fffh 0800h 07ffh 0000h 0000h static page page 1 page 0 4fffh page 1 page 9 static page ... program space rom interrupt & reset vectors accumulator data ram bank select data rom window select ram x register y register v register w register data rom window ram / eeprom banking area 000h 03fh 040h 07fh 080h 081h 082h 083h 084h 0c0h 0ffh 0-63 data space 0000h 0ff0h 0fffh program counter stack level 1 stack level 2 stack level 3 stack level 4 stack level 5 stack level 6 vr01568 stack space rom 07ffh 0800h
10/84 st6365, st6375, st6385 ST6367, st6377, st6387 memory spaces (contd) program rom page register (prpr) address: cah - write only reset value: xxh d7-d4 . these bits are not used but have to be written to 0. prpr3-prpr0. these are the program rom banking bits and the value loaded selects the cor- responding page to be addressed in the lower part of 4k program address space as specified in table 3 . this register is undefined on reset. caution : this register contains at least one write only bit. single bit instructions (set, res, inc and dec) should not be used. note. only the lower part of address space has been bankswitched because interrupt vectors and common subroutines should be available all the time. the reason of this structure is due to the fact that it is not possible to jump from a dynamic page to another, unless jumping back to the static page, changing contents of prpr and then jumping to a different dynamic page. care is required when handling the prpr as it is write only. for this reason, it is not allowed to change the prpr contents while executing inter- rupts drivers, as the driver cannot save and than restore its previous content. anyway, this opera- tion may be necessary if the sum of common rou- tines and interrupt drivers will take more than 2k bytes; in this case it could be necessary to divide the interrupt driver in a (minor) part in the static page (start and end), and in the second (major) part in one dynamic page. if it is impossible to avoid the writing of this register in interrupts driv- ers, an image of this register must be saved in a ram location. each time the program writes the prpr register, the image register should also be written. the image register must be written first, so if an interrupt occurs between the two instructions the prpr is not affected. table 3. program memory page register coding table 4. program memory map 70 - - - - prpr3 prpr2 prpr1 prpr0 prpr3 prpr2 prpr1 prpr0 pc11 memory page xxxx1 static page (page 1) 0 0 0 0 0 page 0 00010 page 1 (static page) 0 0 1 0 0 page 2 0 0 1 1 0 page 3 0 1 0 0 0 page 4 0 1 0 1 0 page 5 0 1 1 0 0 page 6 0 1 1 1 0 page 7 1 0 0 0 0 page 8 1 0 0 1 0 page 9 program memory page device address description page 0 0000h-007fh 0080h-07ffh reserved user rom page 1 static 0800h-0f9fh 0fa0h-0fefh 0ff0h-0ff7h 0ff8h-0ffbh 0ffch-0ffdh 0ffeh-0fffh user rom reserved interrupt vectors reserved nmi vector reset vector page 2 0000h-000fh 0010h-07ffh reserved user rom page 3 0000h-000fh 0010h-07ffh reserved user rom (end of 8k st6365, 67) page 4 0000h-000fh 0010h-07ffh reserved user rom page 5 0000h-000fh 0010h-07ffh reserved user rom page 6 0000h-000fh 0010h-07ffh reserved user rom (end of 14k st6375, 77) page 7 0000h-000fh 0010h-07ffh reserved user rom page 8 0000h-000fh 0010h-07ffh reserved user rom page 9 0000h-000fh 0010h-07ffh reserved user rom (end of 20k st6385, 87)
11/84 st6365, st6375, st6385 ST6367, st6377, st6387 memory spaces (contd) 1.3.3 data space the st6 core instruction set operates on a specif- ic space, referred to as the data space, which contains all the data necessary for the program. figure 6. data space the data space allows the addressing of ram (256 bytes), eeprom (384 bytes), st6 core and peripheral registers, as well as read-only data such as constants and look-up tables. data ram/eeprom/osd bank area 000h 03fh data rom window area 040h 07fh x register 080h y register 081h v register 082h w register 083h data ram 084h 0bfh port a data register 0c0h port b data register 0c1h port c data register 0c2h reserved 0c3h port a direction register 0c4h port b direction register 0c5h port c direction register 0c6h reserved 0c7h interrupt option register 0c8h data rom window register 0c9h program rom page register 0cah reserved 0cbh spi data register 0cch reserved 0cdh 0d1h timer 1 prescaler register 0d2h timer 1 counter register 0d3h timer 1 status/control register 0d4h reserved 0d5h 0d7h watchdog register 0d8h reserved 0d9h timer 2 prescaler register 0dah timer 2 counter register 0dbh timer 2 status/control register 0dch reserved 0ddh 0dfh da 0 data/control register 0e0h da 1 data/control register 0e1h da 2 data/control register 0e2h da 3 data/control register 0e3h afc, ir & osd result register 0e5h output control register 1 0e6h da 4 data/control register 0e7h da 5 data/control register 0e8h dedicated latches control register 0e9h eeprom control register 0eah spi control register 1 0ebh spi control register 2 0ech osd character bank select register 0edh vs data register 1 0eeh vs data register 2 0efh 0f0h reserved 0f5h 0feh accumulator 0ffh osd control registers located in page 6 of banked data ram vertical start address register 010h horizontal start address register 011h vertical space register 012h horizontal space register 013h background colour register 014h global enable register 017h
12/84 st6365, st6375, st6385 ST6367, st6377, st6387 memory spaces (contd) data rom addressing. all the read-only data are physically implemented in the rom in which the program space is also implemented. the rom therefore contains the program to be executed and also the constants and the look-up tables needed for the program. the locations of data space in which the different constants and look-up tables are addressed by the st6 core can be considered as being a 64-byte window through which it is pos- sible to access to the read-only data stored in the rom. this window is located from the 40h ad- dress to the 7fh address in the data space and al- lows the direct reading of the bytes from the 000h address to the 03fh address in the rom. all the bytes of the rom can be used to store either in- structions or read-only data. indeed, the window can be moved by step of 64 bytes along the rom in writing the appropriate code in the write-only data rom window register (drwr, location c9h). the effective address of the byte to be read as a data in the rom is obtained by the concate- nation of the 6 less significant bits of the address in the data space (as less significant bits) and the content of the drwr (as most significant bits). so when addressing location 40h of data space, and 0 is loaded in the drwr, the physical addressed location in rom is 00h. note: the data rom window can not address window above the 16k byte range. data rom window register (drwr) address: c9h - write only reset value: xxh drwr7-drwr0 . these are the data rom win- dow bits that correspond to the upper bits of data rom program space. this register is undefined af- ter reset. caution : this register contains at least one write only bit. single bit instructions (set, res, inc and dec) should not be used. note: care is required when handling the drwr as it is write only. for this reason, it is not allowed to change the drwr contents while executing in- terrupts drivers, as the driver cannot save and than restore its previous content. if it is impossible to avoid the writing of this register in interrupts drivers, an image of this register must be saved in a ram location, and each time the program writes the drwr it writes also the image register. the image register must be written first, so if an inter- rupt occurs between the two instructions the drwr register is not affected. figure 7. data rom window memory addressing 70 drwr 7 drwr 6 drwr 5 drwr 4 drwr 3 drwr 2 drwr 1 drwr 0 data rom window register contents data space address 40h-7fh in instruction program space address 765432 0 543210 543210 read 1 6 7 8 9 10 11 0 1 vr01573b 12 1 0 data space address 59h 0 0 0 0 0 1 00 1 1 1 example: (dwr) dwr=28h 11 0000 0 0 00 1 rom address:a19h 11 13 0 1 0 0
13/84 st6365, st6375, st6385 ST6367, st6377, st6387 memory spaces (contd) 1.3.4 data ram/eeprom/osd ram addressing in all members of the st638x family 64 bytes of data ram are directly addressable in the data space from 80h to bfh addresses. the additional 192 bytes of ram, the 384 bytes of eeprom, and the osd ram can be addressed using the banks of 64 bytes located between addresses 00h and 3fh. the selection of the bank is done by pro- gramming the data ram bank register (drbr) located at the e8h address of the data space. in this way each bank of ram, eeprom or osd ram can select 64 bytes at a time. no more than one bank should be set at a time. data ram bank register (drbr) address: e8h - write only reset value: xxh drbr7,drbr1,drbr0 . these bits select the eeprom pages. drbr6, drbr5 . each of these bits, when set, will select one osd ram register page. drbr4,drbr3,drbr2 . each of these bits, when set, will select oneram page. this register is undefined after reset. table 5 summarizes how to set the data ram bank register in order to select the various banks or pages. caution : this register contains at least one write only bit. single bit instructions (set, res, inc and dec) should not be used. note : care is required when handling the drbr as it is write only. for this reason, it is not allowed to change the drbr contents while executing in- terrupts drivers, as the driver cannot save and than restore its previous content. if it is impossible to avoid the writing of this register in interrupts drivers, an image of this register must be saved in a ram location, and each time the program writes the drbr it writes also the image register. the im- age register must be written first, so if an interrupt occurs between the two instructions the drbr is not affected. table 5. data ram bank register set-up 70 drbr 7 drbr 6 drbr 5 drbr 4 drbr 3 drbr 2 drbr 1 drbr 0 drbr value selection hex. binary 01h 0000 0001 eeprom page 0 02h 0000 0010 eeprom page 1 03h 0000 0011 eeprom page 2 81h 1000 0001 eeprom page 3 82h 1000 0010 eeprom page 4 83h 1000 0011 eeprom page 5 04h 0000 0100 ram page 2 08h 0000 1000 ram page 3 10h 0001 0000 ram page 4 20h 0010 0000 osd page 5 40h 0100 0000 osd page 6
14/84 st6365, st6375, st6385 ST6367, st6377, st6387 memory spaces (contd) eeprom description the data space of st638x family from 00h to 3fh is paged as described in table 5 . 384 bytes of eeprom located in six pages of 64 bytes (pages 0,1,2,3,4 and 5, see table 5 ). through the programming of the data ram bank register (drbr=e8h) the user can select the bank or page leaving unaffected the way to ad- dress the static registers. the way to address the dynamic page is to set the drbr as described in table 5 (e.g. to select eeprom page 0, the drbr has to be loaded with content 01h, see data ram/eeprom/osd ram addressing for additional information). bits 0, 1 and 7 of the drbr are dedicated to the eeprom. the eeprom pages do not require dedicated in- structions to be accessed in reading or writing. the eeprom is controlled by the eeprom con- trol register (eecr=eah). any eeprom location can be read just like any other data location, also in terms of access time. to write an eeprom location takes an average time of 5 ms (10ms max) and during this time the eeprom is not accessible by the core. a busy flag can be read by the core to know the eeprom status before trying any access. in writing the eeprom can work in two modes: byte mode (bmode) and parallel mode (pmode). the bmode is the normal way to use the eeprom and consists in accessing one byte at a time. the pmode consists in accessing 8 bytes per time. eeprom control register (eecr) address: eah - read only/write only reset value: d7 . not used caution : this register contains at least one write only bit. single bit instructions (set, res, inc and dec) should not be used. sb . write only. if this bit is set the eeprom is disabled (any access will be meaningless) and the power consumption of the eeprom is reduced to the leakage values. d5, d4 . reserved for testing purposes, they must be set to zero. ps . write only. once in parallel mode, as soon as the user software sets the ps bit the par- allel writing of the 8 adjacent registers will start. ps is internally reset at the end of the programming procedure. note that less than 8 bytes can be writ- ten; after parallel programming the remaining un- defined bytes will have no particular content. pe . write only. this bit must be set by the user program in order to perform parallel programming (more bytes per time). if pe is set and the parallel start bit (ps) is low, up to 8 adjacent bytes can be written at the maximum speed, the content being stored in volatile registers. these 8 adjacent bytes can be considered as row, whose a7, a6, a5, a4, a3 are fixed while a2, a1 and a0 are the changing bytes. pe is automatically reset at the end of any parallel programming procedure. pe can be reset by the user software before starting the program- ming procedure, leaving unchanged the eeprom registers. bs . read only. this bit will be automatically set by the core when the user program modifies an eeprom register. the user program has to test it before any read or write eeprom operation; any attempt to access the eeprom while busy bit is set will be aborted and the writing procedure in progress completed. en . write only. this bit must be set to one in order to write any eeprom register. if the user program will attempt to write the eeprom when en= 0 the involved registers will be unaffected and the busy bit will not be set. after reset the content of eecr register will be 00h. notes : when the eeprom is busy (bs=1) the eecr can not be accessed in write mode, it is only possible to read bs status. this implies that as long as the eeprom is busy it is not possible to change the status of the eeprom control register. eecr bits 4 and 5 are reserved for test purposes, and must never be set to 1. 70 - sb - - pspebsen
15/84 st6365, st6375, st6385 ST6367, st6377, st6387 memory spaces (contd) additional notes on parallel mode . if the user wants to perform a parallel programming the first action should be the setting of the pe bit; from this moment, the first time the eeprom w ill be ad- dressed in writing, the row address will be latched and it will be possible to change it only at the end of the programming procedure or by reset- ting pe without programming the eeprom. after the row address latching the core can see just one eeprom row (the selected one) and any attempt to write or read other rows will produce errors. do not read the eeprom while pe is set. as soon as pe bit is set, the 8 volatile row latch- es are cleared. from this moment the user can load data in the whole row or just in a subset. ps setting will modify the eeprom registers corre- sponding to the row latches accessed after pe. for example, if the software sets pe and accesses eeprom in writing at addresses 18h,1ah,1bh and then sets ps, these three registers will be modified at the same time; the remaining bytes will have no particular content. note that pe is inter- nally reset at the end of the programming proce- dure. this implies that the user must set pe bit be- tween two parallel programming procedures. any- way the user can set and then reset pe without performing any eeprom programming. ps is a set only bit and is internally reset at the end of the programming procedure. note that if the user tries to set ps while pe is not set there will not be any programming procedure and the ps bit will be un- affected. consequently ps bit can not be set if en is low. ps can be affected by the user set if, and only if, en and pe bits are also set to one.
16/84 st6365, st6375, st6385 ST6367, st6377, st6387 2 central processing unit 2.1 introduction the cpu core of st6 devices is independent of the i/o or memory configuration. as such, it may be thought of as an independent central processor communicating with on-chip i/o, memory and pe- ripherals via internal address, data, and control buses. in-core communication is arranged as shown in figure 8 ; the controller being externally linked to both the reset and oscillator circuits, while the core is linked to the dedicated on-chip pe- ripherals via the serial data bus and indirectly, for interrupt purposes, through the control registers. 2.2 cpu registers the st6 family cpu core features six registers and three pairs of flags available to the program- mer. these are described in the following para- graphs. accumulator (a) . the accumulator is an 8-bit general purpose register used in all arithmetic cal- culations, logical operations, and data manipula- tions. the accumulator can be addressed in data space as a ram location at address ffh. thus the st6 can manipulate the accumulator just like any other register in data space. indirect registers (x, y). these two indirect reg- isters are used as pointers to memory locations in data space. they are used in the register-indirect addressing mode. these registers can be ad- dressed in the data space as ram locations at ad- dresses 80h (x) and 81h (y). they can also be ac- cessed with the direct, short direct, or bit direct ad- dressing modes. accordingly, the st6 instruction set can use the indirect registers as any other reg- ister of the data space. short direct registers (v, w). these two regis- ters are used to save a byte in short direct ad- dressing mode. they can be addressed in data space as ram locations at addresses 82h (v) and 83h (w). they can also be accessed using the di- rect and bit direct addressing modes. thus, the st6 instruction set can use the short direct regis- ters as any other register of the data space. program counter (pc). the program counter is a 12-bit register which contains the address of the next rom location to be processed by the core. this rom location may be an opcode, an oper- and, or the address of an operand. the 12-bit length allows the direct addressing of 4096 bytes in program space. figure 8. st6 core block diagram program reset opcode flag values 2 controller flags alu a-data b-data address/read line data space interrupts data ram/eeprom data rom/eprom results to data space (write line) rom/eprom dedications accumulator control signals oscin oscout address decoder 256 12 program counter and 6 layer stack 0,01 to 8mhz vr01811
17/84 st6365, st6375, st6385 ST6367, st6377, st6387 cpu registers (contd) however, if the program space contains more than 4096 bytes, the additional memory in program space can be addressed by using the program bank switch register. the pc value is incremented after reading the ad- dress of the current instruction. to execute relative jumps, the pc and the offset are shifted through the alu, where they are added; the result is then shifted back into the pc. the program counter can be changed in the following ways: - jp (jump) instruction . . . . . pc=jump address - call instruction . . . . . . . . . pc= call address - relative branch instruction . pc= pc +/- offset - interrupt . . . . . . . . . . . . . .pc=interrupt vector - reset . . . . . . . . . . . . . . . . . pc= reset vector - ret & reti instructions . . . . pc= pop (stack) - normal instruction . . . . . . . . . . . . .pc= pc + 1 flags (c, z) . the st6 cpu includes three pairs of flags (carry and zero), each pair being associated with one of the three normal modes of operation: normal mode, interrupt mode and non maskable interrupt mode. each pair consists of a carry flag and a zero flag. one pair (cn, zn) is used during normal operation, another pair is used dur- ing interrupt mode (ci, zi), and a third pair is used in the non maskable interrupt mode (cnmi, zn- mi). the st6 cpu uses the pair of flags associated with the current mode: as soon as an interrupt (or a non maskable interrupt) is generated, the st6 cpu uses the interrupt flags (resp. the nmi flags) instead of the normal flags. when the reti in- struction is executed, the previously used set of flags is restored. it should be noted that each flag set can only be addressed in its own context (non maskable interrupt, normal interrupt or main rou- tine). the flags are not cleared during context switching and thus retain their status. the carry flag is set when a carry or a borrow oc- curs during arithmetic operations; otherwise it is cleared. the carry flag is also set to the value of the bit tested in a bit test instruction; it also partici- pates in the rotate left instruction. the zero flag is set if the result of the last arithme- tic or logical operation was equal to zero; other- wise it is cleared. switching between the three sets of flags is per- formed automatically when an nmi, an interrupt or a reti instructions occurs. as the nmi mode is automatically selected after the reset of the mcu, the st6 core uses at first the nmi flags. stack. the st6 cpu includes a true lifo hard- ware stack which eliminates the need for a stack pointer. the stack consists of six separate 12-bit ram locations that do not belong to the data space ram area. when a subroutine call (or inter- rupt request) occurs, the contents of each level are shifted into the next higher level, while the content of the pc is shifted into the first level (the original contents of the sixth stack level are lost). when a subroutine or interrupt return occurs (ret or reti instructions), the first level register is shifted back into the pc and the value of each level is popped back into the previous level. since the accumula- tor, in common with all other data space registers, is not stored in this stack, management of these registers should be performed within the subrou- tine. the stack will remain in its deepest position if more than 6 nested calls or interrupts are execut- ed, and consequently the last return address will be lost. it will also remain in its highest position if the stack is empty and a ret or reti is executed. in this case the next instruction will be executed. figure 9. st6 cpu programming mode l short direct addressing mode vregister wregister program counter six levels stack register cz normal flags interrupt flags nmi flags index register va000423 b7 b7 b7 b7 b7 b0 b0 b0 b0 b0 b0 b11 accumulator yreg.pointer xreg.pointer cz cz
18/84 st6365, st6375, st6385 ST6367, st6377, st6387 3 clocks, reset, interrupts and power saving modes 3.1 on-chip clock oscillator the internal oscillator circuit is designed to require a minimum of external components. a crystal quartz, a ceramic resonator, or an external signal (provided to the oscin pin) may be used to gener- ate a system clock with various stability/cost trade- offs. the typical clock frequency is 8mhz. please note that different frequencies will affect the oper- ation of those peripherals (d/as, spi) whose refer- ence frequencies are derived from the system clock. the different clock generator connection schemes are shown in figure 10 and 11 . one machine cycle takes 13 oscillator pulses; 12 clock pulses are needed to increment the pc while and additional 13th pulse is needed to stabilize the internal latch- es during memory addressing. this means that with a clock frequency of 8mhz the machine cycle is 1.625sec. the crystal oscillator start-up time is a function of many variables: crystal parameters (especially rs), oscillator load capacitance (cl), ic parame- ters, ambient temperature, and supply voltage.it must be observed that the crystal or ceramic leads and circuit connections must be as short as possi- ble. typical values for cl1 and cl2 are in the range of 15pf to 22pf but these should be chosen based on the crystal manufacturers specification. typical input capacitance for oscin and oscout pins is 5pf. the oscillator output frequency is internally divided by 13 to produce the machine cycle and by 12 to produce the timers and the watchdog clock. a byte cycle is the smallest unit needed to execute any operation (i.e., increment the program coun- ter). an instruction may need two, four, or five byte cycles to be executed (see table 6 ). table 6. instruction timing with 8mhz clock figure 10. clock generator option 1 figure 11. clock generator option 2 figure 12. oscin, oscout diagram instruction type cycles execution time branch if set/reset 5 cycles 8.125 m s branch & subroutine branch 4 cycles 6.50 m s bit manipulation 4 cycles 6.50 m s load instruction 4 cycles 6.50 m s arithmetic & logic 4 cycles 6.50 m s conditional branch 2 cycles 3.25 m s program control 2 cycles 3.25 m s osc in osc out c l1 c l2 st6xxx crystal/resonator clock va0016b osc in osc out st6xxx external clock nc va0015c va00462 oscout in oscin, oscout (quartz pins) oscin 1m v dd dd v
19/84 st6365, st6375, st6385 ST6367, st6377, st6387 3.2 resets the mcu can be reset in three ways: C by the external reset input being pulled low; C by power-on reset; C by the digital watchdog peripheral timing out. 3.2.1 reset input the reset pin may be connected to a device of the application board in order to reset the mcu if required. the reset pin may be pulled low in run, wait or stop mode. this input can be used to reset the mcu internal state and ensure a correct start-up procedure. the pin is active low and features a schmitt trigger input. the internal reset signal is generated by adding a delay to the external signal. therefore even short pulses on the reset pin are acceptable, provided v dd has completed its rising phase and that the oscillator is running correctly (normal run or wait modes). the mcu is kept in the reset state as long as the reset pin is held low. if reset activation occurs in run or wait modes, processing of the user program is stopped (run mode only), the inputs and outputs are con- figured as inputs with pull-up resistors if available. when the level on the r eset pin t hen goes high, the initialization sequence is executed following expiry of the internal delay period. if reset pin activation occurs in the stop mode, the oscillator starts up and all inputs and outputs are configured as inputs with pull-up resistors if available. when the level of the reset pin then goes high, the initialization sequence is executed following expiry of the internal delay period. 3.2.2 power-on reset the function of the por circuit consists in waking up the mcu at an appropriate stage during the power-on sequence. at the beginning of this se- quence, the mcu is configured in the reset state: all i/o ports are configured as inputs with pull-up resistors and no instruction is executed. when the power supply voltage rises to a sufficient level, the oscillator starts to operate, whereupon an internal delay is initiated, in order to allow the oscillator to fully stabilize before executing the first instruction. the initialization sequence is executed immediate- ly following the internal delay. the internal delay is generated by an on-chip counter. the internal reset line is released 2048 in- ternal clock cycles after release of the external re- set. the internal por device is a static mechanism which forces the reset state when v dd is below a threshold voltage in the range 3.4 to 4.2 volts (see figure 13 ). the circuit guarantees that the mcu will exit or enter the reset state correctly, without spurious effects, ensuring, for example, that eep- rom contents are not corrupted. note : this feature is not available on otp/eprom devices. figure 13. power on/off reset operation figure 14. reset and interrupt processing vr02037 v dd 4.2 3.4 t v t power on/off threshold dd reset int latch cleared nmi mask set reset ( if present ) select nmi mode flags is reset still present? yes put ffeh on address bus from reset locations ffe/fff no fetch instruction load pc va000427
20/84 st6365, st6375, st6385 ST6367, st6377, st6387 resets (contd) 3.2.3 watchdog reset the mcu provides a watchdog timer function in order to ensure graceful recovery from software upsets. if the watchdog register is not refreshed before an end-of-count condition is reached, the internal reset will be activated. this, amongst oth- er things, resets the watchdog counter. the mcu restarts just as though the reset had been generated by the reset pin, including the built-in stabilisation delay period. 3.2.4 application note no external resistor is required between v dd and the reset pin, thanks to the built-in pull-up device. 3.2.5 mcu initialization sequence when a reset occurs the stack is reset, the pc is loaded with the address of the reset vector (locat- ed in program rom starting at address 0ffeh). a jump to the beginning of the user program must be coded at this address. following a reset, the in- terrupt flag is automatically set, so that the cpu is in non maskable interrupt mode; this prevents the initialisation routine from being interrupted. the in- itialisation routine should therefore be terminated by a reti instruction, in order to revert to normal mode and enable interrupts. if no pending interrupt is present at the end of the initialisation routine, the mcu will continue by processing the instruction immediately following the reti instruction. if, how- ever, a pending interrupt is present, it will be serv- iced. figure 15. reset and interrupt processing figure 16. reset circuit reset reset vector jp jp:2 bytes/4 cycles reti reti: 1 byte/2 cycles initialization routine va00181 va0200e to st6 reset st6 internal reset oscillator signal watchdog reset v dd 300k reset (active low) counter 1k power on/off reset
21/84 st6365, st6375, st6385 ST6367, st6377, st6387 3.3 hardware activated digital watchdog function the hardware activated digital watchdog function consists of a down counter that is automatically in- itialized after reset so that this function does not need to be activated by the user program. as the watchdog function is always activated this down counter can not be used as a timer. the watchdog is using one data space register (hwdr location d8h). the watchdog register is set to feh on reset and immediately starts to count down, requiring no software start. similarly the hardware activated watchdog can not be stopped or delayed by soft- ware. the watchdog time can be programmed using the 6 msbs in the watchdog register, this gives the possibility to generate a reset in a time between 3072 to 196608 oscillator cycles in 64 possible steps. (with a clock frequency of 8mhz this means from 384ms to 24.576ms). the reset is prevented if the register is reloaded with the desired value before bits 2-7 decrement from all zeros to all ones. the presence of the hardware watchdog deacti- vates the stop instruction and a wait instruction is automatically executed instead of a stop. bit 1 of the watchdog register (set to one at reset) can be used to generate a software reset if cleared to zero). figure 17 shows the watchdog block dia- gram while figure 18 shows its working principle. figure 17. hardware activated watchdog block diagram rsff 8 data bus va00010 -2 -12 oscillator reset write reset db0 r s q db1.7 set load 7 8 -2 set clock
22/84 st6365, st6375, st6385 ST6367, st6377, st6387 hardware activated digital watchdog function (contd) hardware activated watchdog register (hwdr) address: d8h - read/write reset value: 0feh t1-t6 . these are the watchdog counter bits. it should be noted that d7 (t1) is the lsb of the counter and d2 (t6) is the msb of the counter, these bits are in the opposite order to normal. sr . this bit is set to one during the reset phase and will generate a software reset if cleared to ze- ro. c . this is the watchdog activation bit that is hard- ware set. the watchdog function is always activat- ed independently of changes of value of this bit. the register reset value is feh (bit 1-7 set to one, bit 0 cleared). figure 18. hardware activated watchdog working principle 70 t1 t2 t3 t4 t5 t6 sr c bit0 va00190 bit1 bit2 bit3 bit4 bit5 bit6 bit7 8-bit down counter osc-12 watchdog control register reset d0 d1 d2 d3 d4 d5 d6 d7
23/84 st6365, st6375, st6385 ST6367, st6377, st6387 3.4 interrupt the st638x core can manage 4 different maska- ble interrupt sources, plus one non-maskable in- terrupt source (top priority level interrupt). each source is associated with a particular interrupt vec- tor that contains a jump instruction to the related interrupt service routine. each vector is located in the program space at a particular address (see table 7 ). when a source provides an interrupt re- quest, and the request processing is also enabled by the st638x core, then the pc register is load- ed with the address of the interrupt vector (i.e. of the jump instruction). finally, the pc is loaded with the address of the jump instruction and the interrupt routine is processed. the relationship between vector and source and the associated priority is hardware fixed for the dif- ferent st638x devices. for some interrupt sourc- es it is also possible to select by software the kind of event that will generate the interrupt. all interrupts can be disabled by writing to the gen bit (global interrupt enable) of the interrupt option register (address c8h). after a reset, st638x is in non maskable interrupt mode, so no interrupts will be accepted and nmi flags will be used, until a reti instruction is executed. if an interrupt is exe- cuted, one special cycle is made by the core, dur- ing that the pc is set to the related interrupt vector address. a jump instruction at this address has to redirect program execution to the beginning of the related interrupt routine. the interrupt detecting cycle, also resets the related interrupt flag (not available to the user), so that another interrupt can be stored for this current vector, while its driver is under execution. if additional interrupts arrive from the same source, they will be lost. nmi can interrupt other in- terrupt routines at any time, while other interrupts cannot interrupt each other. if more than one inter- rupt is waiting for service, they are executed ac- cording to their priority. the lower the number, the higher the priority. priority is, therefore, fixed. in- terrupts are checked during the last cycle of an in- struction (reti included). level sensitive inter- rupts have to be valid during this period. 3.4.1 interrupt vectors/sources the st638x core includes 5 different interrupt vectors in order to branch to 5 different interrupt routines. the interrupt vectors are located in the fixed (or static) page of the program space. the interrupt vector associated with the non- maskable interrupt source is named interrupt vec- tor #0. it is located at the (ffch,ffdh) addresses in the program space. this vector is associated with the pc6/irin pin. the interrupt vectors located at addresses (ff6h, ff7h), (ff4h, ff5h), (ff2h, ff3h), (ff0h, ff1h) are named interrupt vectors #1, #2, #3 and #4 re- spectively. these vectors are associated with tim- er 2 (#1), vsync (#2), timer 1 (#3) and pc4(pwrin) (#4). table 7. interrupt vectors/sources relationships note 1 . this pin is associated with the nmi inter- rupt vector 3.4.2 interrupt priority the non-maskable interrupt request has the high- est priority and can interrupt any other interrupt routines at any time, nevertheless the other inter- rupts cannot interrupt each other. if more than one interrupt request is pending, they are processed by the st638x core according to their priority lev- el: vector #1 has the higher priority while vector #4 the lower. the priority of each interrupt source is hardware fixed. interrupt source associated vector vector address pc6/irin pin 1 interrupt vector # 0 (nmi) 0ffch-0ffdh timer 2 interrupt vector # 1 0ff6h-0ff7h vsync interrupt vector #2 0ff4h-0ff5h timer 1 interrupt vector #3 0ff2h-0ff3h pc4/pwrin interrupt vector #4 0ff0h-0ff1h
24/84 st6365, st6375, st6385 ST6367, st6377, st6387 interrupts (contd) 3.4.3 interrupt option register interrupt option register (ior) address: (c8h) - write only reset value: x000xxxxb the interrupt option register (ior register, loca- tion c8h) is used to enable/disable the individual in- terrupt sources and to select the operating mode of the external interrupt inputs. this register can be ad- dressed in the data space as ram location at the c8h address, nevertheless it is a write-only register that can not be accessed with single-bit operations. the operating modes of the external interrupt inputs associated to interrupt vectors #1 and #2 are se- lected through bits 5 and 6 of the ior register. caution : this register contains at least one write only bit. single bit instructions (set, res, inc and dec) should not be used. d7 . not used. el1 . this is the edge/level selection bit of inter- rupt #1. when set to one, the interrupt is generat- ed on low level of the related signal; when cleared to zero, the interrupt is generated on falling edge. the bit is cleared to zero after reset. es2 . this is the edge selection bit on interrupt #2. this bit is used on the st638x devices with on- chip osd generator for vsync detection. when this bit is se to one, the interrupt #2 is positive edge sensitive, when cleared to zero the negative edge sensitive interrupt is selected. gen . this is the global enable bit. when set to one all interrupts are globally enabled; when this bit is cleared to zero all interrupts are disabled (ex- cluding nmi). d3 - d0. these bits are not used. 3.4.4 interrupt procedure the interrupt procedure is very similar to a call pro- cedure; the user can consider the interrupt as an asynchronous call procedure. as this is an asyn- chronous event the user does not know about the context and the time at which it occurred. as a result the user should save all the data space registers which will be used inside the interrupt routines. there are separate sets of processor flags for nor- mal, interrupt and non-maskable interrupt modes which are automatically switched and so these do not need to be saved. the following list summarizes the interrupt proce- dure (refer also to figure 19 *) C interrupt detection C the flags c and z of the main routine are ex- changed with the flags c and z of the interrupt routine (resp. the nmi flags) C the value of the pc is stored in the first level of the stack - the normal interrupt lines are inhibit- ed (nmi still active) C the edge flip-flop is reset C the related interrupt vector is loaded in the pc. C user selected registers are saved inside the in- terrupt service routine (normally on a software stack) C the source of the interrupt is found by polling (if more than one source is associated to the same vector) C interrupt servicing C return from interrupt (reti) C automatically the st638x core switches back to the normal flags (resp the interrupt flags) and pops the previous pc value from the stack figure 19. interrupt processing flow-chart 70 - el1 es2 gen ---- instruction fetch instruction execute instruction was the instruction a reti ? ? clear interrupt mask select program flags pop the stacked pc ? check if there is an interrupt request and interrupt mask select internal mode flag push the pc into the stack load pc from interrupt vector (ffc/ffd) set interrupt mask no no yes is the core already in normal mode? va000014 yes no yes
25/84 st6365, st6375, st6385 ST6367, st6377, st6387 interrupts (contd) the interrupt routine begins usually by the identifi- cation of the device that has generated the inter- rupt request. the user should save the registers which are used inside the interrupt routine (that holds relevant data) into a software stack. after the reti instruction execution, the core carries out the previous actions and the main routine can con- tinue. 3.4.5 st638x interrupt details ir interrupt (#0). the irin/pc6 interrupt is con- nected to the first interrupt #0 (nmi, 0ffch). if the irint interrupt is disabled at the latch circuitry, then it will be high. the #0 interrupt input detects a high to low level. note that once #0 has been latched, then the only way to remove the latched #0 signal is to service the interrupt. #0 can inter- rupt the other interrupts. a simple latch is provided from the pc6(irin) pin in order to generate the ir- int signal. this latch can be triggered by either the positive or negative edge of irint signal. ir- int is inverted with respect to the latch. the latch can be read by software and reset by software. timer 2 interrupt (#1). the timer 2 interrupt is connected to the interrupt #1 (0ff6h). the timer 2 interrupt generates a low level (which is latched in the timer). only the low level selection for #1 can be used. bit 6 of the interrupt option register c8h has to be set. vsync interrupt (#2). the vsync interrupt is connected to the interrupt #2. when disabled the vsync int signal is low. the vsync int signal is inverted with respect to the signal applied to the vsync pin. bit 5 of the interrupt option register c8h is used to select the negative edge (es2=0) or the positive edge (es2=1); the edge will depend on the application. note that once an edge has been latched, then the only way to remove the latched signal is to service the interrupt. care must be taken not to generate spurious interrupts. this interrupt may be used to synchronize the vsync signal in order to change characters in the osd only when the screen is on vertical blanking (if de- sired). this method may also be used to blink characters. timer 1 interrupt (#3). the timer 1 interrupt is connected to the fourth interrupt #3 (0ff2h) which detects a low level (latched in the timer). pwr interrupt (#4). the pwr interrupt is con- nected to the fifth interrupt #4 (0ff0h). if the pwrint is disabled at the pwr circuitry, then it will be high. the #4 interrupt input detects a low level. a simple latch is provided from the pc4 (pwrin)pin in order to generate the pwrint sig- nal. this latch can be triggered by either the posi- tive or negative edge of the pwrin signal. pwrint is inverted with respect to the latch. the latch can be reset by software. notes: global disable does not reset edge sensi- tive interrupt flags. these edge sensitive interrupts become pending again when global disabling is re- leased. moreover, edge sensitive interrupts are stored in the related flags also when interrupts are globally disabled, unless each edge sensitive in- terrupt is also individually disabled before the in- terrupting event happens. global disable is done by clearing the gen bit of interrupt option register, while any individual disable is done in the control register of the peripheral. the on-chip timer pe- ripherals have an interrupt request flag bit (tmz), this bit is set to one when the device wants to gen- erate an interrupt request and a mask bit (eti) that must be set to one to allow the transfer of the flag bit to the core.
26/84 st6365, st6375, st6385 ST6367, st6377, st6387 3.5 power saving modes stop and wait modes have been implemented in the st638x in order to reduce the current con- sumption of the device during idle periods. these two modes are described in the following para- graphs. since the hardware activated digital watchdog function is present, the stop instruc- tion is de-activated and any attempt to execute it will cause the automatic execution of a wait in- struction. 3.5.1 wait mode the configuration of the mcu in the wait mode occurs as soon as the wait instruction is execut- ed. the microcontroller can also be considered as being in a software frozen state where the core stops processing the instructions of the routine, the contents of the ram locations and peripheral registers are saved as long as the power supply voltage is higher than the ram retention voltage but where the peripherals are still working. the wait mode is used when the user wants to re- duce the consumption of the mcu when it is in idle, while not losing count of time or monitoring of external events. the oscillator is not stopped in or- der to provide clock signal to the peripherals. the timers counting may be enabled (writing the psi bit in tscr1 register) and the timer interrupt may be also enabled before entering the wait mode; this allows the wait mode to be left when timer in- terrupt occurs. if the exit from the wait mode is performed with a general reset (either from the activation of the external pin or by watchdog reset) the mcu will enter a normal reset procedure as described in the r eset chapter. if an interrupt is generated during wait mode the mcu behaviour depends on the state of the mcu core before the initialization of the wait sequence, but also of the kind of the interrupt request that is generated. this case will be described in the following paragraphs. in any case, the mcu core does not generate any delay after the occurrence of the interrupt because the oscillator clock is still available. 3.5.2 stop mode since the hardware activated watchdog is present on the st638x, the stop instruction has been de- activated. any attempt to execute a stop instruc- tion will cause a wait instruction to be executed instead. 3.5.3 exit from wait mode the following paragraphs describe the output pro- cedure of the mcu core from wait mode when an interrupt occurs. it must be noted that the re- start sequence depends on the original state of the mcu (normal, interrupt or non-maskable interrupt mode) before the start of the wait sequence, but also of the type of the interrupt request that is gen- erated. in all cases the gen bit of ior has to be set to 1 in order to restart from wait mode. con- trary to the operation of nmi in the run mode, the nmi is masked in wait mode if gen=0. normal mode . if the mcu core was in the main routine when the wait instruction has been exe- cuted, the core exits from wait mode as soon as an interrupt occurs; the corresponding interrupt routine is executed, and at the end of the interrupt service routine, the instruction that follows the wait instruction is executed if no other interrupts are pending. non-maskable interrupt mode . if the wait in- struction has been executed during the execution of the non-maskable interrupt routine, the mcu core outputs from wait mode as soon as any in- terrupt occurs: the instruction that follows the wait instruction is executed and the mcu core is still in the non-maskable interrupt mode even if an- other interrupt has been generated. normal interrupt mode . if the mcu core was in the interrupt mode before the initialization of the wait sequence, it outputs from the wait mode as soon as any interrupt occurs. nevertheless, two cases have to be considered: C if the interrupt is a normal interrupt, the interrupt routine in which the wait was entered will be completed with the execution of the instruction that follows the wait and the mcu core is still in the interrupt mode. at the end of this routine pending interrupts will be serviced in accordance to their priority. C if the interrupt is a non-maskable interrupt, the non-maskable routine is processed at first. then, the routine in which the wait was entered will be completed with the execution of the instruction that follows the wait and the mcu core is still in the normal interrupt mode. notes : if all the interrupt sources are disabled, the restart of the mcu can only be done by a reset activa- tion. the wait instruction is not executed if an en- abled interrupt request is pending. in st638x de- vices, the hardware activated digital watchdog function is present. as the watchdog is always ac- tivated, the stop instruction is de-activated and any attempt to execute the stop instruction will cause an execution of a wait instruction.
27/84 st6365, st6375, st6385 ST6367, st6377, st6387 4 on-chip peripherals 4.1 i/o ports the st638x microcontrollers use three standard i/ o ports (a,b,c) with up to eight pins on each port; refer to the device pin configurations to see which pins are available. each line can be individually programmed either in the input mode or the output mode as follows by software. C output C input with on-chip pull-up resistor (selected by software) C input without on-chip pull-up resistor (selected by software) note : pins with 12v open-drain capability do not have pull-up resistors. in output mode the following hardware configura- tions are available: C open-drain output 12v (pa4-pa7, pc4-pc7) C open-drain output 5v (pc0-pc3) C push-pull output (pa0-pa3, pb0-pb6) the lines are organized in three ports (port a,b,c). the ports occupy 6 registers in the data space. each bit of these registers is associated with a par- ticular line (for instance, the bits 0 of the port a data and direction registers are associated with the pa0 line of port a). there are three data registers (dra, drb, drc), that are used to read the voltage level values of the lines programmed in the input mode, or to write the logic value of the signal to be output on the lines con- figured in the output mode. the port data registers can be read to get the effective logic levels of the pins, but they can be also written by the user soft- ware, in conjunction with the related data direction register, to select the different input mode options. single-bit operations on i/o registers (bit set/reset instructions) are possible but care is necessary be- cause reading in input mode is made from i/o pins and therefore might be influenced by the external load, while writing will directly affect the port data register causing an undesired changes of the input configuration. the three data direction registers (ddra, ddrb, ddrc) allow the selection of the di- rection of each pin (input or output). all the i/o registers can be read or written as any other ram location of the data space, so no extra ram cell is needed for port data storing and ma- nipulation. during the initialization of the mcu, all the i/o registers are cleared and the input mode with pull-up is selected on all the pins thus avoiding pin conflicts (with the exception of pc2 that is set in out- put mode and is set high i.e. high impedance).
28/84 st6365, st6375, st6385 ST6367, st6377, st6387 i/o ports (contd) 4.1.1 details of i/o ports when programmed as an input a pull-up resistor (if available) can be switched active under program control. when programmed as an output the i/o port will operate either in the push-pull mode or the open-drain mode according to the hardware fixed configuration as specified below. port a . pa0-pa3 are available as push-pull when outputs. pa4-pa7 are available as open-drain (no push-pull programmability) capable of withstand- ing 12v (no resistive pull-up in input mode). pa6- pa7 has been specially designed for higher driving capability and are able to sink 25ma with a maxi- mum vol of 1v. port b . all lines are configured as push-pull when outputs. port c . pc0-pc3 are available as open-drain ca- pable of withstanding a maximum vdd+0.3v. pc4-pc7 are avail-able as open-drain capable of withstanding 12v (no resistive pull-up in input mode). some lines are also used as i/o buffers for signals coming from the on-chip spi. in this case the final signal on the output pin is equivalent to a wired and with the programmed data output. if the user needs to use the serial peripheral, the i/ o line should be set in output mode while the open-drain configuration is hardware fixed; the corresponding data bit must set to one. if the latched interrupt functions are used (irin, pwrin) then the corresponding pins should be set to input mode. on st638x the i/o pins with double or special functions are: C pc0/scl (connected to the spi clock signal) C pc1/sda (connected to the spi data signal) C pc3/sen (connected to the spi enable signal) C pc4/pwrin (connected to the pwrin interrupt latch) C pc6/irin (connected to the irin interrupt latch) all the port a,b and c i/o lines have schmitt-trig- ger input configuration with a typical hysteresis of 1v. table 8. i/o port options selection (ports a and b only) note x : means dont care. ddr dr mode option 0 0 input with on-chip pull-up resistor 0 1 input without on-chip pull-up resistor 1 x output output open-drain or push-pull
29/84 st6365, st6375, st6385 ST6367, st6377, st6387 i/o ports (contd) table 9. i/o port option selections note 1 . provided the correct configuration has been selected. mode available on (1) schematic input pa0-pa7 pb0-pb2 pb4-pb6 pc0-pc7 input with pull up pa0-pa3 pb0-pb2 pb4-pb6 pc0-pc3 open drain output 5v open drain output 5ma / 12v pc0-pc3 pa4-pa7 pc4-pc7 push-pull output 5ma push-pull output 10ma pb0-pb2 pb4-pb6 pa0-pa3 data in data in data out data out vdd vdd vdd vdd
30/84 st6365, st6375, st6385 ST6367, st6377, st6387 i/o ports (contd) 4.1.2 i/o pin programming each pin can be individually programmed as input or output with different input and output configura- tions. this is achieved by writing to the relevant bit in the data (dr) and data direction register (ddr). table 10 shows all the port configurations that can be selected by the user software. 4.1.3 input/output configurations the table 9 shows the i/o lines hardware configu- ration for the different options. notes : the wait instruction allows the st638x to be used in situations where low power consump- tion is needed. this can only be achieved however if the i/o pins either are programmed as inputs with well defined logic levels or have no power consuming resistive loads in output mode. as the same die is used for the different st638x versions the unavailable i/o lines of st638x should be pro- grammed in output mode. single-bit operations on i/o registers are possible but care is necessary because reading in input mode is made from i/o pins while writing will di- rectly affect the port data register causing an un- desired changes of the input configuration. table 10. i/o port options selection (port c) note : x. means dont care. 4.1.4 i/o port registers 4.1.4.1 data registers ports a, b, c data register address : c0h (pa), c1h (pb), c2h (pc) - read/ write reset value: 00h pa7-pa0 . these are the i/o port a data bits. re- set at power-on. pb7-pb0 . these are the i/o port b data bits. re- set at power-on. pc7-pc0 . set to 04h at power-on. bit 2 (pc2 pin) is set to one (open drain therefore high imped- ance). 4.1.4.2 data direction registers port a, b, c data direction register address: c4h (pa), c5h (pb), c6h (pc) - read/ write reset value:00h pa7-pa0 . these are the i/o port a data direction bits. when a bit is cleared to zero the related i/o line is in input mode, if bit is set to one the related i/o line is in output mode. reset at power-on. pb7-pb0 . these are the i/o port b data direction bits. when a bit is cleared to zero the related i/o line is in input mode, if bit is set to one the related i/o line is in output mode. reset at power-on. pc7-pc0 . these are the i/o port c data direction bits. when a bit is cleared to zero the related i/o line is in input mode, if bit is set to one the related i/o line is in output mode. set to 04h at power-on. bit 2 (pc2 pin) is set to one (output mode select- ed). ddr dr mode option 0 0 input with on-chip pull-up resistor 0 1 input without on-chip pull-up resistor 1 x output open-drain 70 pa/ pb/ pc7 pa/ pb/ pc6 pa/ pb/ pc5 pa/ pb/ pc4 pa/ pb/ pc3 pa/ pb/ pc2 pa/ pb/ pc1 pa/ pb/ pc0 70 pa/ pb/ pc7 pa/ pb/ pc6 pa/ pb/ pc5 pa/ pb/ pc4 pa/ pb/ pc3 pa/ pb/ pc2 pa/ pb/ pc1 pa/ pb/ pc0
31/84 st6365, st6375, st6385 ST6367, st6377, st6387 4.2 timers the st638x devices offer two on-chip timer pe- ripherals consisting of an 8-bit counter with a 7-bit programmable prescaler, thus giving a maximum count of 2 15 , and a control logic that allows config- uration the peripheral operating mode. figure 20 shows the timer block diagram. the content of the 8-bit counters can be read/written in the timer/ counter registers tcr that are addressed in the data space as ram locations at addresses d3h (timer 1), dbh (timer 2). the state of the 7-bit prescaler can be read in the psc register at ad- dresses d2h (timer 1) and dah (timer 2). the control logic is managed by tscr registers at d4h (timer 1) and dch (timer 2) addresses as de- scribed in the following paragraphs. the following description applies to all timers. the 8-bit counter is decrement by the output (rising edge) coming from the 7-bit prescaler and can be loaded and read under program control. when it decrements to zero then the tmz (timer zero) bit in the tscr is set to one. if the eti (enable timer in- terrupt) bit in the tscr is also set to one an inter- rupt request, associated to interrupt vector #3 for timer 1 and #1 for timer 2, is generated. the in- terrupt of the timer can be used to exit the mcu from the wait mode. the prescaler decrements on rising edge. the prescaler input is the oscillator frequency divided by 12. depending on the division factor pro- grammed by ps2/ps1/ps0 (see table 11 ) bits in the tscr, the clock input of the timer/counter reg- ister is multiplexed to different sources. on divi- sion factor 1, the clock input of the prescaler is also that of timer/counter; on factor 2, bit 0 of pres- caler register is connected to the clock input of tcr. this bit changes its state with the half frequency of prescaler clock input. on factor 4, bit 1 of psc is connected to clock input of tcr, and so on. on di- vision factor 128, the msb bit 6 of psc is connect- ed to clock input of tcr. the prescaler initialize bit (psi) in the tscr register must be set to one to al- low the prescaler (and hence the counter) to start. if it is cleared to zero then all of the prescaler bits are set to one and the counter is inhibited from counting.the prescaler can be given any value be- tween 0 and 7fh by writing to the related register address, if bit psi in the tscr register is set to one. the tap of the prescaler is selected using the ps2/ps1/ps0 bits in the control register. figure 21 illustrates the timer working principle. figure 20. timer peripheral block diagram databus 8 8 8 8 8-bit counter 6 5 4 3 2 1 0 psc status/control register b7 b6 b5 b4 b3 b2 b1 b0 tmz eti tout dout psi ps2 ps1 ps0 select 1 of 8 3 latch synchronization logic timer interrupt line va00009 : 12 f osc
32/84 st6365, st6375, st6385 ST6367, st6377, st6387 timers (contd) 4.2.1 timer operating modes since in the st638x devices the external timer pin is not connected, the only allowed operating mode is the output mode, which is selected by set- ting bit 4 and by clearing bit 5 in the tscr1 regis- ter. this procedure will enable timer 1 and timer 2. output mode (tscr1 d4 = 1, tscr1 d5 = 0) . on this mode the timer prescaler is clocked by the prescaler clock input (osc/12). the user can se- lect the desired prescaler division ratio through the ps2/ps1/ps0 bits. when tcr count reaches 0, it sets the tmz bit in the tscr. the tmz bit can be tested under program control to perform timer functions whenever it goes high. bits d4 and d5 on tscr2 (timer 2) register are not implemented. timer interrupt when the counter register decrements to zero and the software controlled eti (enable timer interrupt) bit is set to one then an interrupt request associat- ed to interrupt vector #3 (for timer 1), to interrupt vector #1 (for timer 2) is generated. when the counter decrements to zero also the tmz bit in the tscr register is set to one. notes: tmz is set when the counter reaches 00h; howev- er, it may be set by writing 00h in the tcr register or setting the bit 7 of the tscr register. tmz bit must be cleared by user software when servicing the timer interrupt to avoid undesired interrupts when leaving the interrupt service routine. after re- set, the 8-bit counter register is loaded to ffh while the 7-bit prescaler is loaded to 7fh, and the tscr register is cleared which means that timer is stopped (psi=0) and timer interrupt disabled. a write to the tcr register will predominate over the 8-bit counter decrement to 00h function, i.e. if a write and a tcr register decrement to 00h occur simultaneously, the write will take precedence, and the tmz bit is not set until the 8-bit counter reaches 00h again. the values of the tcr and the psc registers can be read accurately at any time. figure 21. timer working principle bit0 bit1 bit2 bit3 bit6 bit5 bit4 clock 7-bit prescaler 8-1 multiplexer 8-bit counter bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 1 02 3 4 5 67 ps0 ps1 ps2 va00186
33/84 st6365, st6375, st6385 ST6367, st6377, st6387 timers (contd) 4.2.2 timer status control registers (tscr) timers 1 and 2 address: d4h (timer 1), dch (timer 2) - read/ write reset value: 00h tmz . low-to-high transition indicates that the tim- er count register has decremented to zero. this bit must be cleared by user software before to start with a new count. eti . this bit, when set, enables the timer interrupt (vector #3 for timer 1, vector #2 for timer 2 re- quest). if eti=0 the timer interrupt is disabled. if eti= 1 and tmz= 1 an interrupt request is gener- ated. d5 . this is the timers enable bit d5. it must be cleared to 0 together with a set to 1 of bit d4 to en- able timer 1 and timer 2 functions. it is not imple- mented on registers tscr2. d4 . this is the timers enable bit d4. this bit must be set to 1 together with a clear to 0 of bit d5 to en- able all timers (timer 1 and 2) functions. it is not implemented on registers tscr2. psi . used to initialize the prescaler and inhibit its counting while psi = 0 the prescaler is set to 7fh and the counter is inhibited. when psi = 1 the prescaler is enabled to count downwards. as long as psi= 0 both counter and prescaler are not run- ning. ps2-ps0 . these bits select the division ratio of the prescaler register. (see table 11) the tscr1 and tscr2 registers are cleared on reset. the correct d4-d5 combination must be written in tscr1 by user's software to enable the operation of timer 1 and 2. table 11. prescaler division factors 4.2.3 timer counter registers (tcr) timer counter 1 and 2 address: d3h (timer counter 1), dbh (timer counter 2) - read/write reset value: ffh bit 7-0 = d7-d0 : counter bits. 4.2.4 timer prescaler registers (pscr) timer prescalers 1 and 2 address: d2h (timer prescaler 1), dah (timer prescaler 2) - read/write reset value: 7fh bit 7 = d7 : always read as "0". bit 6-0 = d6-d0 : prescaler bits. 70 tmz eti d5 d4 psi ps2 ps1 ps0 d5 d4 timers 0 0 disabled 0 1 enabled 1 x reserved ps2 ps1 ps0 divided by 000 1 001 2 010 4 011 8 10016 10132 11064 111128 70 d7 d6 d5 d4 d3 d2 d1 d0 70 d7 d6 d5 d4 d3 d2 d1 d0
34/84 st6365, st6375, st6385 ST6367, st6377, st6387 4.3 serial peripheral interface the st638x serial peripheral interface (spi) has been designed to be cost effective and flexible in interfacing the various peripherals in tv applica- tions. it maintains the software flexibility but adds hard- ware configurations suitable to drive devices which require a fast exchange of data. the three pins dedicated for serial data transfer (single mas- ter only) can operate in the following ways: C as standard i/o lines (software configuration) C as s-bus or as i 2 c bus (two pins) C as standard (shift register) spi when using the hardware spi, a fixed clock rate of 62.5khz is provided. it has to be noted that the first bit that is output on the data line by the 8-bit shift register is the msb. 4.3.1 s-bus/i 2 c bus protocol information the s-bus is a three-wire bidirectional data-bus with functional features similar to the i 2 c bus. in fact the s-bus includes decoding of start/stop conditions and the arbitration procedure in case of multimaster system configuration (the st638x spi allows a single-master only operation). the sda line, in the i 2 c bus represents the and combina- tion of sda and sen lines in the s-bus. if the sda and the sen lines are short-circuit connect- ed, they appear as the sda line of the i 2 c bus. the start/stop conditions are detected (by the ex- ternal peripherals suited to work with s-bus/i 2 c bus) in the following way: C on s-bus by a transition of the senline (1 to 0 start, 0 to 1 stop) while the scl line is at high level. C on i 2 c bus by a transition of the sda line (10 start, 01stop) while the scl line is at high level. start and stop condition are always generated by the master (st638x spi can only work as single master). the bus is busy after the start condition and can be considered again free only when a cer- tain time delay is left after the stop condition. in the s-bus configuration the sda line is only allowed to change during the time scl line is low. after the start information the senline returns to high level and re-mains unchanged for all the data transmis- sion time. when the transmission is completed the sda line is set to high level and, at the same time, the sen line returns to the low level in order to supply the stop in-formation with a low to high tran- sition, while the scl line is at high level. on the s- bus, as on the i 2 c bus, each eight bit information (byte) is followed by one acknowledged bit which is a high level put on the sda line by the transmit- ter. a peripheral that acknowledges has to pull down the sda line during the acknowledge clock pulse. an addressed receiver has to generate an acknowledge after the reception of each byte; oth- erwise the sda line remains at the high level dur- ing the ninth clock pulse time. in this case the mas- ter transmitter can generate the stop condition, via the sen (or sda in i 2 c bus) line, in order to abort the transfer.
35/84 st6365, st6375, st6385 ST6367, st6377, st6387 serial peripheral interface (contd) start/stop acknowledge . the timing specs of the s-bus protocol require that data on the sda (only on this line for i 2 c bus) and sen lines be stable during the high time of scl. two exceptions to this rule are foreseen and they are used to signal the start and stop condition of data transfer. C on s-bus by a transition of the sen line (10 start, 01 stop) while the scl line is at high level. C on i 2 c bus by a transition of the sda line (10 start, 01 stop) while the scl line is at high level. data are transmitted in 8-bit groups; after each group, a ninth bit is interposed, with the purpose of acknowledging the transmitting sequence (the transmit device place a 1 on the bus, the ac- knowledging receiver a 0). interface protocol. this paragraph deals with the description of data protocol structure. the inter- face protocol includes: C a start condition C a slave chip address byte, transmitted by the master, containing two different information: a. the code identifying the device the master wants to address (this information is present in the first seven bits) b. the direction of transmission on the bus (this information is given in the 8th bit of the byte); 0 means write, that is from the master to the slave, while 1 means read. the addressed slave must always acknowledge. the sequence from, now on, is different according to the value of r/w bit. 1. r/w = 0 (write) in all the following bytes the master acts as trans- mitter; the sequence follows with: a. an optional data byte to address (if needed) the slave location to be written (it can be a word address in a memory or a register address, etc.). b. a data byte which will be written at the address given in the previous byte. c. further data bytes. d. a stop condition a data transfer is always terminated by a stop con- dition generated from the master. the st638x pe- ripheral must finish with a stop condition before another start is given. figure 22 shows an exam- ple of write operation. 2. r/w = 1 (read) in this case the slave acts as transmitter and, therefore, the transmission direction is changed. in read mode two different conditions can be consid- ered: a. the master reads slave immediately after first byte. in this case after the slave address sent from the master with read condition enabled the master transmitter becomes master receiver and the slave receiver becomes slave transmit- ter. b. the master reads a specified register or loca- tion of the slave. in this case the first sent byte will contain the slave address with write condi- tion enabled, then the second byte will specify the address of the register to be read. at this moment a new start is given together with the slave address in read mode and the procedure will proceed as described in previous point a.
36/84 st6365, st6375, st6385 ST6367, st6377, st6387 serial peripheral interface (contd) figure 22. i2c master transmit to slave receiver (write mode) figure 23. i2c master reads slave immediately after first byte (read mode) figure 24. i2c master reads after setting slave register address (write address, read data) word address slave address soaa ap acknowledge from slave msb start r/w stop data acknowledge from slave acknowledge from slave slave address s1aa 1p acknowledge from slave msb start r/w stop data acknowledge from master no acknowledge from master msb n bytes data slave address s word address a p acknowledge from slave start r/w stop slave address s1aa 1p acknowledge from slave msb start r/w stop data acknowledge from master no acknowledge from master msb data 0a x acknowledge from slave
37/84 st6365, st6375, st6385 ST6367, st6377, st6387 serial peripheral interface (contd) 4.3.2 s-bus/i 2 c bus timing diagrams the clock of the s-bus/i 2 c bus of the st638x spi (single master only) has a fixed bus clock fre- quency of 62.5khz. all the devices connected to the bus must be able to follow transfers with fre- quencies up to 62.5khz, either by being able to transmit or receive at that speed or by applying the clock synchronization procedure which will force the master into a wait state and stretch low peri- ods. figure 25. s-bus timing diagram va00454 034 1 scl sen (transmit) sda (transmit) sda pulled low by receiver if acknowledged. ^ ^ ^ ^ ^ ^ sda pulled low by spi peripheral. sda (receive) sen (receive) sen (start) sda (start) ^ ^ ^ sda pulled low by receiver if acknowledged. sen (stop) sda (stop) ^ ^ ^ sda pulled low by receiver if acknowledge. if in receive then there will be no ack. by the spi. scl scl 2 16a 7 5 57a 6 12 1 4 3 0 57a 6 12 1 4 3 0
38/84 st6365, st6375, st6385 ST6367, st6377, st6387 serial peripheral interface (contd) figure 26. i 2 c bus timing diagram note : the third pin, sen, should be high; it is not used in the i 2 c bus. logically sda is the and of the s-bus sda and sen.) va00455 023 16a 7 5 scl sda (transmit) sda pulled low by receiver if acknowledged. sda pulled low by spi peripheral. sda (receive) sda (start) sda pulled low by receiver if acknowledged. sda (stop) sda pulled low by receiver if acknowledge. if in receive then there will be no ack. by the spi. scl scl 57a 6 14 3 2 0 57a 6 14 3 2 0
39/84 st6365, st6375, st6385 ST6367, st6377, st6387 serial peripheral interface (contd) 4.3.3 compatibility s-bus/i 2 c bus using the s-bus protocol it is possible to imple- ment mixed system including s-bus/i 2 c bus bus peripherals. in order to have the compatibility with the i 2 c bus peripherals, the devices including the s-bus interface must have their sda and sen pins connected together as shown in the following figure 27 (a and b). it is also possible to use mixed s-bus/i 2 c bus protocols as showed in figure 27 (c). s-bus peripherals will only react to s-bus protocol signals, while i 2 c bus peripherals will only react to i 2 c bus signals. multimaster config- uration is not possible with the st63xx spi (single master only). figure 27. s-bus/ i 2 c bus mixed configurations scl sda sen st6 s-bus protocol scl sda sen i 2 c-bus slave scl sda scl sda sen st6 i 2 c-bus protocol scl sda sen i 2 c-bus slave scl sda scl sda sen st6 protocol scl sda sen i 2 c-bus slave scl sda s-bus/i 2 c-bus va00457 va00456 va00452 a b c
40/84 st6365, st6375, st6385 ST6367, st6377, st6387 serial peripheral interface (contd) 4.3.4 std spi protocol (shift register) this protocol is similar to the i 2 c bus with the ex- ception that there is no acknowledge pulse and there are no stop or start bits. the clock cannot be slowed down by the external peripherals. in this case all three outputs should be high in or- der not to lock the software i/os from functioning. spi standard bus protocol: the standard bus pro- tocol is selected by loading the spi control regis- ter 1 (scr1 add. ebh). bit 0 named i2c must be set at one and bit 1 named std must be reset. when the standard bus protocol is selected bit 2 of the scr1 is meaningless. this bit named stop bit is used only in i 2 c bus or sbus. however take care that the stop bit must be reset when the standard pro- tocol is used. this bit is set to zero after re- set. figure 28. software bus (hardware bus disabled) timing diagram 4.3.5 spi data/control register for i/o details on scl (serial clock), sda (serial data) and sen (serial enable) please refer to i/o ports description with reference to the following registers: port c data register, address c2h (read/write). - bit d0 scl - bit d1 sda - bit d3 sen port c data direction register, address c6h (read/ write). spi serial data register (ssdr) address: cch - read/write reset value: xxh ssdr7-0 . these are the spi data bits. they can be neither read nor written when spi is operating (busy bit set). they are undefined after reset. va00453 0 234 167 5 ident (was sen, this is optionally controlled by software; output as far as hardware is concerned is high). clock (was scl) data (was sda, transmit) data (was sda, receive) 70 ssdr 7 ssdr 6 ssdr 5 ssdr 4 ssdr 3 ssdr 2 ssdr 1 ssdr 0
41/84 st6365, st6375, st6385 ST6367, st6377, st6387 serial peripheral interface (contd) spi control register 1 (scr1) address: ebh - write only reset value: 00h caution : this register contains at least one write only bit. single bit instructions (set, res, inc and dec) should not be used. b7-b4. these bits are not used. str . this is start bit for i 2 c bus/s-bus. this bit is meaningless when std/spi enable bit is cleared to zero. if this bit is set to one and std/spi bit is also set to 1 then spi start generation, be- fore beginning of transmission, is enabled. set to zero after reset. stp . this is stop bit for i 2 c bus/s-bus. this bit is meaningless when std/spi enable bit is cleared to zero. if this bit is set to one and std/spi bit is also set to 1 then spi stop condition gener- ation is enabled. stp bit must be reset when standard protocol is used (this is also the default reset conditions). set to zero after reset. std, spi enable. this bit, in conjunction with s- bus/i 2 c bus bit, allows the spi disable and will select between i 2 c bus/s-bus and standard shift register protocols. if this bit is set to one, it se- lects both i 2 c bus and s-bus protocols; final se- lection between them is made by s-bus/i 2 c bus bit. if this bit is cleared to zero when s-bus/i 2 c bus is set to 1 the standard shift register proto- col is selected. if this bit is cleared to 0 when s- bus/i 2 c bus is cleared to 0 the spi is disabled. set to zero after reset. s-bus/i 2 c bus selection . this bit, in conjunction with std/spi bit, allows the spi disable and will select between i 2 c bus and s-bus protocols. if this bit is cleared to 0 when std bit is also 0, the spi interface is disabled. if this bit is cleared to zero when std bit is set to 1, the i 2 c bus proto- col will be selected. if this bit is set to 1 when std bit is set to 1, the s-bus protocol will be se- lected. cleared to zero after reset. table 12. spi mode selection spi control register 2 (scr2) address: ech - read/write reset value: 00h caution : this register contains at least one write only bit. single bit instructions (set, res, inc and dec) should not be used. b7-b4 . these bits are not used. tx/rx . write only. when this bit is set, current byte operation is a transmission. when it is reset, current operation is a reception. set to zero after reset. vry/s . read only/write only. this bit has two dif- ferent functions in relation to read or write opera- tion. reading operation: when std and/or trx bits is cleared to 0, this bit is meaningless. when bits std and tx are set to 1, this bit is set each time bsy bit is set. this bit is reset during byte op- eration if real data on sda line are different from the output from the shift register. set to zero after reset. writing operation: it enables (if set to one) or disables (if cleared to zero) the interrupt coming from vsync pin. undefined after reset. refer to osd description for additional information. acn . read only. if std bit (d1 of scr1 register) is cleared to zero this bit is meaningless. when std is set to one, this bit is set to one if no ac- knowledge has been received. in this case it is au- tomatically reset when bsy is set again. set to zero after reset. bsy . read/set only. this is the busy bit. when a one is loaded into this bit the spi interface start the transmission of the data byte loaded into ssdr data register or receiving and building the receive data into the ssdr data register. this is done in accordance with the protocol, direction and start/ stop condition(s). this bit is automatically cleared at the end of the current byte operation. cleared to zero after reset. note : the spi shift register is also the data trans- mission register and the data received register; this feature is made possible by using the serial structure of the st638x and thus reducing size and complexity. 70 ----strstp std/ spi s-bus/ i 2 cbus d1 std/sp d0 s-bus/i 2 c bus spi function 0 0 disabled 0 1 std shift reg. 10i 2 c bus 1 1 s-bus 70 ----tx/rxvry/sacnbsy
42/84 st6365, st6375, st6385 ST6367, st6377, st6387 serial peripheral interface (contd) during transmission or reception of data, all ac- cess to serial data register is therefore disabled. the reception or transmission of data is started by setting the busy bit to 1; this will be automatical- ly reset at the end of the operation. after reset, the busy bit is cleared to 0, and the hardware spi disabled by clearing bit 0 and bit 1 of spi control register 1 to 0. the outputs from the hardware spi are anded to the standard i/o software con- trolled outputs. if the hardware spi is in operation the port c pins related to the spi should be config- ured as outputs using the data direction register and should be set high. when the spi is config- ured as the s-bus, the three pins pc0, pc1 and pc3 become the pins scl, sda and sen respec- tively. when configured as the i 2 c bus the pins pc0 and pc1 are configured as the pins scl and sda; pc3 is not driven and can be used as a gen- eral purpose i/o pin. in the case of the std spi the pins pc0 and pc1 become the signals clock and data, pc3 is not driven and can be used as general purpose i/o pin. the verify bit is availa- ble when the spi is configured as either s-bus or i 2 c bus. at the start of a byte transmission, the verify bit is set to one. if at any time during the transmission of the following eight bits, the data on the sda line does not match the data forced by the spi (while scl is high), then the verify bit is re- set. the verify is available only during transmis- sion for the s-bus and i 2 c bus; for other protocol it is not defined. the sda and scl signal entering the spi are buffered in order to remove any minor glitches. when std bit is set to one (s-bus or i 2 c bus selected), and trx bit is reset (receiving da- ta), and stop bit is set (last byte of current com- munication), the spi interface does not generate the acknowledge, according to s-bus/i 2 c bus specifications. pco-scl, pc1-sda and pc3- sen lines are standard drive i/o port pins with open-drain output configuration (maximum voltage that can be applied to these pins is v dd + 0.3v).
43/84 st6365, st6375, st6385 ST6367, st6377, st6387 4.4 14-bit voltage synthesis tuning peripheral the st638x on-chip voltage synthesis tuning pe- ripheral has been integrated to allow the genera- tion of tuning reference voltage in low/mid end tv set applications. the peripheral is composed of a 14-bit counter that allows the conversion of the digital content in a tuning voltage, available at the vs output pin, by using pulse width modification (pwm), and bit rate multiplier (brm) techniques. the 14-bit counter gives 16384 steps which allows a resolution of approximately 2mv over a tuning voltage of 32v; this corresponds to a tuning reso- lution of about 40khz per step in the uhf band (the actual value will depend on the characteristics of the tuner). the tuning word consists of a 14-bit word con- tained in the registers vsdata1 (location 0eeh) and vsdata2 (location 0efh). coarse tuning (pwm) is performed using the seven msbits, while fine tuning (brm) is performed using the data in the seven lsbits. with all zeros loaded the output is zero; as the tuning voltage increases from all zeros, the number of pulses in one period increase to 128 with all pulses being the same width. for values larger than 128, the pwm takes over and the number of pulses in one period re- mains constant at 128, but the width changes. at the other end of the scale, when almost all ones are loaded, the pulses will start to link together and the number of pulses will decrease. when all ones are loaded, the output will be almost 100% high but will have a low pulse (1/16384 of the high pulse). 4.4.1 output details inside the on-chip voltage synthesis are included the register latches, a reference counter, pwm and brm control circuitry. in the st638x the clock for the 14-bit reference counter is 2mhz derived from the 8mhz system clock. from the circuit point of view, the seven most significant bits control the coarse tuning, while the seven least significant bits control the fine tuning. from the application and software point of view, the 14 bits can be consid- ered as one binary number. as already mentioned the coarse tuning consists of a pwm signal with 128 steps; we can consider the fine tuning to cover 128 coarse tuning cycles. the addition of pulses is described in the following table. table 13. . fine tuning pulse addition the vs output pin has a standard drive push-pull output configuration. 4.4.2 vs tuning cell registers voltage synthesis data register 1 (vsdr1) address: eeh - write only reset value: xxh caution : this register contains at least one write only bit. single bit instructions (set, res, inc and dec) should not be used. d7-d0 . these are the 8 least significant vs data bits. bit 0 is the lsb. this register is undefined on reset. voltage synthesis data register 2 (vsdr2) address: efh - write only reset value: xxh caution : this register contains at least one write only bit. single bit instructions (set, res, inc and dec) should not be used. d7-d6 . these bits are not used. d5-d0 . these are the 6 most significant vs data bits. bit 5 is the msb. this register is undefined on reset. fine tuning (7 lsb) n of pulses added at the following cycles (0... 127) 0000001 64 0000010 32, 96 0000100 16, 48, 80, 112 0001000 8, 24,....104, 120 0010000 4, 12,....116, 124 0100000 2, 6,.....122, 126 1000000 1, 3,.....125, 127 70 vsdr1 7 vsdr1 6 vsdr1 5 vsdr1 4 vsdr1 3 vsdr1 2 vsdr1 1 vsdr1 0 70 -- vsdr2 5 vsdr2 4 vsdr2 3 vsdr2 2 vsdr2 1 vsdr2 0
44/84 st6365, st6375, st6385 ST6367, st6377, st6387 4.5 6-bit pwm d/a converters the d/a macrocell contains up to six pwm d/a outputs (31.25khz repetition, da0-da5) with six bit resolution. each d/a converter of st638x is composed by the following main blocks: C pre-divider C 6-bit counter C data latches and compare circuits the pre-divider uses the clock input frequency (8mhz typical) and its output clocks the 6-bit free- running counter. the data latched in the six regis- ters (e0h, e1h, e2h, e3h, e6h and e7h) control the six d/a outputs (da0,1,2, 3, 4 and 5). when all zeros are loaded the relevant output is an high log- ic level; all 1's correspond to a pulse with a 1/64 duty cycle and almost 100% zero level. the repetition frequency is 31.25khz and is relat- ed to the 8mhz clock frequency. use of a different oscillator frequency will result in a different repeti- tion frequency. all d/a outputs are open-drain with standard current drive capability and able to with- stand up to 12v. da0-da5 data/control register (dadcr) address: e0h, e1h, e2h, e3h, e4h, e5h, e6h, e7h, - write only reset value: xxh caution : this register contains at least one write only bit. single bit instructions (set, res, inc and dec) should not be used. dadcr0-dadcr5. these are the 6 bits of the pwm digital to analog converter. undefined after reset. figure 29. 6-bit pwm d/a output configuration 70 -- dadcr 5 dadcr 4 dadcr 3 dadcr 2 dadcr 1 dadcr 0 da0-da5 out n out va00343 (open-drain, 12v)
45/84 st6365, st6375, st6385 ST6367, st6377, st6387 4.6 afc a/d comparator the afc macrocell contains an a/d comparator with five levels at intervals of 1v from 1v to 5v. the levels can all be lowered by 0.5v to effectively double the resolution. 4.6.1 a/d comparator the a/d used to perform the afc function (when high threshold is selected) has the following volt- age levels: 1,2,3,4 and 5v. bits 0-2 of afc result register (e4h address) will provide the result in bi- nary form (less than 1v is 000, greater than 5v is 101). if the application requires a greater resolution, the sensitivity can be doubled by clearing to zero bit 2 of the outputs control register, address e5h. in this case all levels are shifted lower by 0.5v. if the two results are now added within a software rou- tine then the a/d s-curve can be located within a resolution of 0.5v. the a/d input has high impedance able to with- stand up to 13v signals (input level tolerances 200mv absolute and 100mv relative to 5v). figure 30. afc input configuration afc, ir and osd result register (afcr) address: e4h - read only reset value: 00h d7-d5. these bits are not used. vsync . this bit reads the status of the vsync pin. it is inverted with respect to the pin. ir. this bit reads the status of the ir latch. if a sig- nal has been latched this bit will be high. ad2-ad0. these bits store the real time conver- sion of the value present on the afc input pin. un- defined reset value. afc shift register (afsr) address: e4h - write only reset value: 00h d7, d6, d5, d4, d3, d1, d0 . these bits are not used. adcr3. this bit determines the voltage range of the afc input. writing a zero will select the 0.5v to 4.5v range. writing a one will select the 1.0v to 5.0v range. undefined after reset. caution : this register contains at least one write only bit. single bit instructions (set, res, inc and dec) should not be used. va00458 afc a in afc (input, high impedance) 70 - - - vsync ir ad2 ad1 ad0 70 -----adsr3--
46/84 st6365, st6375, st6385 ST6367, st6377, st6387 4.7 dedicated latches two latches are available which may generate in- terrupts to the st638x core. the ir latch is set ei- ther by the falling or rising edge of the signal on pin pc6(irin). if bit 1 (irposedge) of the latches register (e9h) is high, then the latch will be trig- gered on the rising edge of the signal at pc6(irin). if bit 1 (irposedge) is low, then the latch will be triggered on the falling edge of the sig- nal at pc6(irin). the ir latch can be reset by set- ting bit 3 (resirlat) of the latches register; the bit is write only and a high should be written every time the ir latch needs to be reset. if bit 2 (irint- en) of the latches register (e9h) is high, then the output of the ir latch, irintn, may generate an in- terrupt (#0). irintn is inverted with respect to the state of the ir latch. if bit 2 (irinten) is low, then the output of the ir latch, irintn, is forced high.the state of the ir latch may be read from bit 3 (irlatch) of register e4h; if the ir latch is set, then bit 3 will be high. the pwr latch is set either by the falling or rising edge of the signal on pin pc4(pwrin). if bit 4 (pwredge) of the latches register (e9h) is high, then the latch will be trig- gered on the rising edge of the signal at pc4(pwrin). if bit 4 (pwredge) is low, then the latch will be triggered on the falling edge of the sig- nal at pc4(pwrin). the pwr latch can be reset by setting bit 6 (respwrlat) of the latches reg- ister; the bit is set only and a high should be written every time the pwr latch needs to be reset. if bit 5 (pwrinten) of the latches register (e9h) is high, then the output of the pwr latch, pwrintn, may generate an interrupt (#4). pwrintn is inverted with respect to the state of the pwr latch. if bit 5 (pwrinten) is low, then the output of the pwr latch, pwrintn, is forced high. dedicated latches control register (dlcr) address: e9h - write only reset value: xxh caution : this register contains at least one write only bit. single bit instructions (set, res, inc and dec) should not be used. d7 . this bit is not used respwrlat . resets the pwr latch; this bit is write only. pwrinten . this bit enables the pwrint signal (#4) from the latch to the st638x core. undefined after reset. pwredge . the bit determines the edge which will cause the pwrin latch to be set. if this bit is high, than the pwrin latch will be set on the rising edge of the pwrin signal. undefined after reset. resirlat . resets the ir latch; this bit is write on- ly. undefined after reset. irinten . this bit enables the irintn signal (#0) from the latch to the st638x core. undefined after reset. irposedge . the bit determines the edge which will cause the ir latch to be set. if this bit is high, than the ir latch will be set on the rising edge of the ir signal. undefined after reset. d0 . this bit is not used 70 - resp- wrlat pwrint- en pwred ge resir- lat irint- en ir- posed ge -
47/84 st6365, st6375, st6385 ST6367, st6377, st6387 4.8 on-screen display (osd) the st638x osd macrocell is a cmos lsi char- acter generator which enable display of characters and symbols on the tv screen. the character rounding function enhances the readability of the characters. the st638x osd receives horizontal and vertical synchronization signal and outputs screen information via r, g, b and blanking pins. the main characteristics of the macrocell are list- ed below C number of display characters: 5 lines by 15 col- umns. C number of character types: 128 characters in two banks of 64 characters. only one bank per screen can be used. C character size: four character heights (18h, 36h, 54h, 72h), two heights are available per screen, programmable by line. C character format: 6 x 9 dots with character rounding function. C character colour: eight colours available pro- grammable by word. C display position: 64 horizontal positions by 2/ f osc and 63 vertical positions by 4h C word spacing: 64 positions programmable from 2/f osc to 128/f osc . C line spacing: 63 positions programmable from 4 to 252 h. C background: no background, square back- ground or fringe background programmable by word. C background colour: two of eight colours availa- ble programmable by word. C display output: three character data output ter- minals (r,g,b) and a blank output terminal. C display on/off: display data may be programmed on or off by word or entire screen. the entire screen may be blanked. 4.8.1 format specification the entire display can be turned on or off through the use of the global enable bit or the display may be selectively turned on or off by word. to turn off the entire display, the global enable bit (ge) should be zero. if the global enable is one, the dis- play is controlled by the word enable bits (we). the global enable bit is located in the global ena- ble register. the word enable bit is located in the space character preceding the word. each line must begin with a format character which describes the format of that line and of the first word. this character is not displayed. a space character defines the format of subse- quent words. a space character is denoted by a one in bit 6 in the display ram. if bit 6 of the dis- play ram is a zero, the other six bits define one of the 64 display characters. the colour, background and enable can be pro- grammed by word. this information is encoded in the space character between words or in the for- mat character at the beginning of each line. five bits define the colour and background of the fol- lowing word, and determine whether it will be dis- played or not. characters are stored in a 6 x 9 dot format. one dot is defined vertically as 2h (horizontal lines) and horizontally as 2/f osc if the smallest character size is enabled. there is no space between char- acters or lines if the vertical space enable (vse) and horizontal space enable (hse) bits are both zero. this allows the use of special graphics char- acters. the normal alphanumeric character set is format- ted to be 5 x 7 with one empty row at the top and one at the bottom and one empty column at the right. if vse and hse are both zero, then the spacing between alphanumeric characters is 1 dot and the spacing between lines of alphanumeric characters is 2h. the character size is programmed by line through the use of the size bit (s) in the format character and the global size bits (gs1 and gs2). the verti- cal spacing enable bit ( vse) located in the format character controls the spacing between lines. if this bit is set to one, the spacing between lines is defined by the vertical spacing register, otherwise the spacing between lines is 0. the spacing between words is controlled by the horizontal space enable bit (hse) located in the space character. if this bit is set to one, the spac- ing between words is defined by the horizontal spacing register, otherwise the space character width of 6 dots is the spacing between words. the formats for the display character, space char- acter and format character are described hereaf- ter.
48/84 st6365, st6375, st6385 ST6367, st6377, st6387 on-screen display (contd) space character register (scr) see data ram table description for specific ad- dress - write only caution : this register contains at least one write only bit. single bit instructions (set, res, inc and dec) should not be used. d7 . not used. d6 . this pin is fixed to 1. r, g, b. colour. the 3 colour control bits define the foreground colour of the following word as shown in table below. table 14. space character register colour setting bgs . background select . the background select bit selects the desired background colour for the following word. there are two possible back- grounds defined by the bits in the background control register. 0 - the background on the following word is ena- bled by bg0 and the colour is set by r0, g0, and b0. 1 -the background on the following word is ena- bled by bg1 and the colour is set by r1, g1, and b1. we. word enable . the word enable bit defines whether or not the following word is displayed. 0 - the word is not displayed. 1 -if the global enable bit is one, then the word is displayed. hse . horizontal space enable . the horizontal space enable bit determines the spacing between words. the space between characters is always 0. the alphanumeric character set is implemented in a 5 x 7 format with one empty column to the right and one empty row above and below so that the space between alphanumeric characters will be one dot. 0 - the space between words is equal to the width of the space character, which is 6 dots. 1 - the space between words is defined by the value in the horizontal space register plus the width of the space character. format character register (fcr) see data ram table description for specific ad- dress - write only caution : this register contains at least one write only bit. single bit instructions (set, res, inc and dec) should not be used. d7 . this bit is not used s . character size . the character size bit, along with the global size bits (gs2 and gs1) located in the horizontal space register, specify the character size for each line as defined in table 16 . r, g, b. colour . the 3 colour control bits define the foreground colour of the following word as shown in table 15 . bgs . background select . the background select bit selects the desired background for the following word. there are two possible backgrounds defined by the bits in the background control register. 0 - the background on the following word is ena- bled by bg0 and the colour is set by r0, g0, and b0. 1 - the background on the following word is ena- bled by bg1 and the colour is set by r1, g1, and b1. we . word enable . the word enable bit defines whether or not the following word is displayed. 0 - the word is not displayed. 1 - if the global enable bit is one, then the word is displayed. vse . vertical space enable . the vertical space enable bit determines the spacing between lines. 0 - the space between lines is equal to 0h. the alphanumeric character set is implemented in a 5 x 7 format with one empty column to the right and one empty row above and one below and stored in a 6 x 9 format. 1 - the space between lines is defined by the value in the vertical space register. 70 -1rg bbgswehse r g b colour 0 0 0 black 0 0 1 blue 0 1 0 green 0 1 1 cyan 1 0 0 red 1 0 1 magenta 1 1 0 yellow 1 1 1 white 70 - s r g b bgs we vse
49/84 st6365, st6375, st6385 ST6367, st6377, st6387 on-screen display (contd) table 15. format character register colour setting. table 16. format character register size display character register (dcr) see data ram table description for specific ad- dress - write only caution : this register contains at least one write only bit. single bit instructions (set, res, inc and dec) should not be used. d7 . this bit is not used. d6 . this bit is fixed to 0. c5-c0. character type . the 6 character type bits define one of the 64 available character types. these character types are shown on the following pages. character types the character set is user defined as rom mask option. register and ram addressing the osd contains seven registers and 80 ram lo- cations. the seven registers are the vertical start address register, horizontal start address regis- ter, vertical space register, horizontal space reg- ister, background control register, global enable register and character bank select register. the global enable register can be written at any time by the st63 core. the other six registers and the ram can only be read or written to if the global en- able is zero. the six registers and the ram are located on two pages of the paged memory of the st638x mcus; the character bank select register is located out- side the paged memory at address edh. each page contains 64 memory locations. this paged memory is at memory locations 00h to 3fh in the st638x memory map. a page of memory is ena- bled by setting the desired page bit, located in the data ram bank register, to a one. the page reg- ister is location e8h. a one in bit five selects page 5, located on the osd and a one in bit 6 selects page 6 on the osd. table 17 shows the address- es of the osd registers and ram. table 17. osd control registers and data ram addressing r g b colour 0 0 0 black 0 0 1 blue 0 1 0 green 0 1 1 cyan 1 0 0 red 1 0 1 magenta 1 1 0 yellow 1 1 1 white gs2 gs1 s vertical height horizontal length 0 0 0 18h 6 tdot 0 0 1 36h 12 tdot 0 1 0 18h 6 tdot 0 1 1 54h 18 tdot 1 0 0 36h 12 tdot 1 0 1 54h 18 tdot 1 1 0 36h 12 tdot 1 1 1 72h 24 tdot 70 - 0 c5 c4 c3 c2 c1 c0 page address register or ram 5 00h - 3fh ram locations 00h - 3fh 6 00h - 0fh ram locations 00h - 0fh 6 10h vertical start register 6 11h horizontal start register 6 12h vertical space register 6 13h horizontal space register 6 14h background control register 6 17h global enable register no page edh character bank select register
50/84 st6365, st6375, st6385 ST6367, st6377, st6387 on-screen display (contd) osd global enable register (oger) address: 17h, page 6 - write only caution : this register contains at least one write only bit. single bit instructions (set, res, inc and dec) should not be used. this register contains the global enable bit (ge). it is the only register that can be written at any time regardless of the state of the ge bit. it is a write only register. vertical start address register (vsar) address: 10h, page 6 - write only caution : this register contains at least one write only bit. single bit instructions (set, res, inc and dec) should not be used. d7-d1 . these bits are not used ge . global enable . this bit allows the entire dis- play to be turned off. 0 - the entire display is disabled. the ram and other registers of the osd can be accessed by the core. 1 - display of words is controlled by the word enable bits (we) located in the format or space character. the other registers and ram cannot be accessed by the core. d7 . this bit is not used fr . fringe background . this bit changes the background from a box background to a fringe background. the background is enabled by word as defined by either bg0 or bg1. 0 - the background is defined to be a box which is 7 x 9 dots. 1 - the background is defined to be a fringe. vsa5-vsa0 . vertical start address. these bits determine the start position of the first line in the vertical direction. the 6 bits can specify 63 display start positions of interval 4h. the first start position will be the fourth line of the display. the vertical start address is defined vsa0 by the following for- mula. vertical start address = 4h(25(vsa5) + 24(vsa4) + 23(vsa3) + 22(vsa2) + 21(vsa1) + 20(vsa0)) the case of all vertical start address bits being zero is illegal. horizontal start address register (hsar) address: 11h, page 6 - write only caution : this register contains at least one write only bit. single bit instructions (set, res, inc and dec) should not be used. d7 . this bit is not used. sbd . space blanking disable . this bit controls whether or not the background is displayed when outputing spaces. if two background colours are used on adjacent words, then the background should not be displayed on spaces in order to make a nice break between colours. if an even background around an area of text is desired, as in a menu, then the background should be displayed when outputing spaces. 0 - the background during spaces is controlled by the background enable bits (bg0 and bg1) located in the background control register. 1 - the background is not displayed when out- puting spaces. hsa5, hsa0 - horizontal start address bits . these bits determine the start position of the first character in the horizontal direction. the 6 bits can specify 64 display start positions of interval 2/f osc or 400ns. the first start position will be at 4.0ms because of the time needed to access ram and rom before the first character can be displayed. the horizontal start address is defined by the fol- lowing formula. horizontal start address = 2/f osc (10.0 + 25(hsa5) + 24(hsa4) + 23(hsa3) + 22(hsa2) + 21(hsa1) + 20(hsa0)) 70 -------ge 70 - fr vsa5 vsa4 vsa3 vsa2 vsa1 vsa0 70 - sbd hsa5 hsa4 hsa3 hsa2 hsa1 hsa0
51/84 st6365, st6375, st6385 ST6367, st6377, st6387 on-screen display (contd) vertical space register (vsr) address: 12h, page 6 - write only reset value: xxh caution : this register contains at least one write only bit. single bit instructions (set, res, inc and dec) should not be used. d7. this bit is not used scb . screen blanking . this bit allows the entire screen to be blanked. 0" - the blanking output signal (vblk) is active only when displaying characters. 1" - the blanking output signal (vblk) is always active. characters in the display ram are still displayed. when this bit is set to one, the screen is blanked also without setting the global enable bit to one (osd disabled). vs5, vs0 . vertical space . these bits determine the spacing between lines if the vertical space en- able bit (vse) in the format character is one. if vse is zero there will be no spaces between lines. the vertical space bits can specify one of 63 spacing values from 4h to 252h. the space be- tween lines is defined by the following formula. space between lines = 4h(25(vs5) + 24(vs4) + 23(vs3) + 22(vs2) + 21(vs1) + 20(vs0)) the case of all vertical start address bits being zero is illegal. horizontal space register (hsr) address: 13h, page 6 - write only reset value: xxh caution : this register contains at least one write only bit. single bit instructions (set, res, inc and dec) should not be used. gs2,gs1 . global size . these bits along with the size bit (s) located in the character format word specify the character size for each line as defined in table 18 . table 18. horizontal space register size setting note : tdot=2/f osc hs5, hs0 . horizontal space . these bits deter- mine the spacing between words if the horizontal space enable bit (hse) located in the space char- acter is a one. the space between words is then equal to the width of the space character plus the number of dots specified by the horizontal space bits. the 6 bits can specify one of 64 spacing val- ues ranging from 2/f osc to 128/f osc . the formula is shown below for the smallest size charac- ter(18h). if larger size characters are being dis- played the spacing between words will increase proportionately. multiply the value below by 2, 3 or 4 for character sizes of 36h, 54h and 72h respec- tively. space between words (not including the space character)=2/f osc (1+25(hs5)+24(hs4)+23(hs3) +22(hs2)+ 21(hs1)+20(hs0)) 70 - scb vs5 vs4 vs3 vs2 vs1 vs0 70 gs2 gs1 hs5 hs4 hs3 hs2 hs1 hs0 gs2 gs1 s vertical height horizontal length 0 0 0 18h 6 tdot 0 0 1 36h 12 tdot 0 1 0 18h 6 tdot 0 1 1 54h 18 tdot 1 0 0 36h 12 tdot 1 0 1 54h 18 tdot 1 1 0 36h 12 tdot 1 1 1 72h 24 tdot
52/84 st6365, st6375, st6385 ST6367, st6377, st6387 on-screen display (contd) background control register (bcr) address 14h, page 6 - write only caution : this register contains at least one write only bit. single bit instructions (set, res, inc and dec) should not be used. this register sets up two possible backgrounds. the background select bit (bgs) in the format or space character will determine which background is selected for the current word. r1,r0,g1,g0,b1,b0. background colour.these bits define the colour of the specified background, either background 1 or background 0 as defined in table below. bk1,bk0 . background enable.these bits deter- mine if the specified background is enabled or not. 0 - the following word does not have a back- ground. 1 - there is a background around the following word. table 19. background register colour setting character bank select register (cbsr) address edh, no page - write only reset value: xxh caution : this register contains at least one write only bit. single bit instructions (set, res, inc and dec) should not be used. d7-d1 . these bits are not used bs . bank select. this bit select the character bank to be used. the lower bank is selected with 0. the value can be modified only when the osd is off (ge=0). no reset value. 70 r1 r0 g1 g0 b1 b0 bk1 bk0 rx gx bx colour 0 0 0 black 0 0 1 blue 0 1 0 green 0 1 1 cyan 1 0 0 red 1 0 1 magenta 1 1 0 yellow 1 1 1 white 70 -------bs
53/84 st6365, st6375, st6385 ST6367, st6377, st6387 on-screen display (contd) osd data ram the contents of the data ram can be accessed by the st638x mcus only when the global enable bit (ge) in the global enable register is a zero. the first character in every line is the format char- acter. this character is not displayed. it defines the size of the characters in the line and contains the vertical space enable bit. this character also defines the colour, background and display enable for the first word in the line. subsequent charac- ters are either spaces or one of the 64 available character types. the space character defines the colour, back- ground, display enable and horizontal space ena- ble for the following word. since there are 5 dis- play lines of 15 characters each, the display ram must contain 5 lines x (15 characters + 1 format character) or 80 locations. the ram size is 80 lo- cations x 7 bits. the data ram map is shown in table 20 . table 20. osd ram map notes : ft. the format character required for each line. characters in columns 1 through 15 are displayed. ch. (byte) character (index into osd character generator) or space character column 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 a0 0 10 1010101010101 a1 0 01 1001100110011 a2 0 00 01111000011 1 1 a3 0 000000111111111 page a5 a4 line 5 0 0 1 ft ch ch ch ch ch ch ch ch ch ch ch ch ch ch ch 5 0 1 2 ft ch ch ch ch ch ch ch ch ch ch ch ch ch ch ch 5 1 0 3 ft ch ch ch ch ch ch ch ch ch ch ch ch ch ch ch 5 1 1 4 ft ch ch ch ch ch ch ch ch ch ch ch ch ch ch ch 6 0 0 5 ft ch ch ch ch ch ch ch ch ch ch ch ch ch ch ch available screen space
54/84 st6365, st6375, st6385 ST6367, st6377, st6387 on-screen display (contd) emulator remarks there are a few differences between emulator and silicon. for noise reasons, the osd oscillator pins are not available: the internal oscillator cannot be disabled and replaced by an external coil. in the emulator, the character bank select register can be written also with global enable bit set, while this is not allowed in the device. application notes 1 - the osd character generator is composed of a dual port video ram and some circuitry. it needs two input signals vsync and hsync to synchro- nize its dedicated oscillator to the tv picture. it generates 4 output signals, that can be used from the tv set to generate the characters on the screen. for instance, they can be used to feed the scart plug, providing an adequate buffer to drive the low impedance (75 w ) of the scart inputs. 2 - the core sees the osd as a number of ram locations (80) plus a certain number of control reg- isters (6). these 86 locations are mapped in two pages of the dynamic data ram address range (0h.3fh). in page 5 (load 20h in the register 0e8h), there are 64 bytes of ram, the ones of the first 4 rows (16 bytes each row, 15 characters per row maximum, plus an hidden leading format charac- ter). in page 6 (load 40h in register 0e8h), the 16 bytes of the fifth row (0..0fh), and the 6 control registers (10h..14h,17h). 3 - the video ram is a dual port ram. that means that it can be addressed either from the core or from the osd circuitry itself. to reduce the com- plexity of the circuitry, and thus its cost, some re- strictions have been introduced in the use of the osd. a. the core can only write to any of the 86 loca- tions (either video ram or control registers). b. the core can only write to any of the leading 85 locations when the osd oscillator is off. only the last location (control register 17h in page 6) can be addressed at any time. this is the global enable register, which contains only the ge bit. if it is set, the osd is on, if it is reset the osd is off. 4 - the timing of the on/off switching of the osd oscillator is the following: a. ge bit is set. the osd oscillator will start on the next vsync signal. b. ge bit is reset. the osd oscillator will be imme- diately switched off. 5 - to avoid a bad visual impression, it is important that the ge bit is set before the end of the flyback time when changing characters. this can be done inside the vsync interrupt routine. the following diagram can explain better: figure 31. osd oscillator on/off timing notes : a - picture time: 20 ms in pal/secam. b - vsync interrupt, if enabled. c - starting of osd oscillator, if ge = 1 d - flyback time. time vsync b v c v e v a d va00344
55/84 st6365, st6375, st6385 ST6367, st6377, st6387 on-screen display (contd) when modifying the picture display (i.e.: a bar graph for an analog control), it is important that the switching on of the ge bit is done before the end of the flyback time (d in figure 31 ). if the ge bit is set after the end of the flyback time then the osd will not start until the beginning of the next frame. this results in one frame being lost and will result in a flicker on the screen. one method to be sure to avoid the flicker is to wait for the vsync inter- rupt at the start of the flyback; once the vsync in- terrupt is detected, then the ge bit can be set to zero, the characters changed, and the ge set to one. all this should occur before the end of the fly- back time in order not to lose a frame. the correct edge of the interrupt must be chosen. the vsync pin may alternatively be sampled by software in or- der to know the status; this can be done by reading bit 4 of register e4h; this bit is inverted with respect to the vsync pin. 6 - an osd end of line bar is present in the st638x rom, eprom and otp devices when using the box background mode. the bar appears at the end of the line in the back- ground mode when the last character is a space character, the first format character is defined with s=0 (size 0)and the box background is not dis- played during the space. the bar is the colour of the background defined by the space character. to eliminate the bar: a. if two backgrounds are used then the bar should be moved off the screen by using large word spaces instead of character spaces. if there are not enough spaces before the end of the line, then the location of the valid characters should be moved so they appear at the end of the line (and hence no bar); positioning can be compensated using the horizontal start register. b. if only one background is used, then the other background should be disabled in order to elim- inate the bar. 7 - the osd oscillator external network should consist of a capacitor on each of the osd oscilla- tor pins to ground together with an inductance be- tween pins. the user should select the two capac- itors to be the same value (15pf to 25pf each is recommended). the inductance is chosen to give the desired osd oscillator frequency for the appli- cation (typically 56h).
56/84 st6365, st6375, st6385 ST6367, st6377, st6387 on-screen display (contd) figure 32. standard osd character set (up code)
57/84 st6365, st6375, st6385 ST6367, st6377, st6387 5 software 5.1 st6 architecture the st6 software has been designed to fully use the hardware in the most efficient way possible while keeping byte usage to a minimum; in short, to provide byte efficient programming capability. the st6 core has the ability to set or clear any register or ram location bit of the data space with a single instruction. furthermore, the program may branch to a selected address depending on the status of any bit of the data space. the carry bit is stored with the value of the bit when the set or res instruction is processed. 5.2 addressing modes the st6 core offers nine addressing modes, which are described in the following paragraphs. three different address spaces are available: pro- gram space, data space, and stack space. pro- gram space contains the instructions which are to be executed, plus the data for immediate mode in- structions. data space contains the accumulator, the x,y,v and w registers, peripheral and input/ output registers, the ram locations and data rom locations (for storage of tables and con- stants). stack space contains six 12-bit ram cells used to stack the return addresses for subroutines and interrupts. immediate . in the immediate addressing mode, the operand of the instruction follows the opcode location. as the operand is a rom byte, the imme- diate addressing mode is used to access con- stants which do not change during program execu- tion (e.g., a constant used to initialize a loop coun- ter). direct . in the direct addressing mode, the address of the byte which is processed by the instruction is stored in the location which follows the opcode. di- rect addressing allows the user to directly address the 256 bytes in data space memory with a single two-byte instruction. short direct . the core can address the four ram registers x,y,v,w (locations 80h, 81h, 82h, 83h) in the short-direct addressing mode. in this case, the instruction is only one byte and the selection of the location to be processed is contained in the op- code. short direct addressing is a subset of the di- rect addressing mode. (note that 80h and 81h are also indirect registers). extended . in the extended addressing mode, the 12-bit address needed to define the instruction is obtained by concatenating the four less significant bits of the opcode with the byte following the op- code. the instructions (jp, call) which use the extended addressing mode are able to branch to any address of the 4k bytes program space. an extended addressing mode instruction is two- byte long. program counter relative . the relative address- ing mode is only used in conditional branch in- structions. the instruction is used to perform a test and, if the condition is true, a branch with a span of -15 to +16 locations around the address of the rel- ative instruction. if the condition is not true, the in- struction which follows the relative instruction is executed. the relative addressing mode instruc- tion is one-byte long. the opcode is obtained in adding the three most significant bits which char- acterize the kind of the test, one bit which deter- mines whether the branch is a forward (when it is 0) or backward (when it is 1) branch and the four less significant bits which give the span of the branch (0h to fh) which must be added or sub- tracted to the address of the relative instruction to obtain the address of the branch. bit direct . in the bit direct addressing mode, the bit to be set or cleared is part of the opcode, and the byte following the opcode points to the ad- dress of the byte in which the specified bit must be set or cleared. thus, any bit in the 256 locations of data space memory can be set or cleared. bit test & branch . the bit test and branch ad- dressing mode is a combination of direct address- ing and relative addressing. the bit test and branch instruction is three-byte long. the bit iden- tification and the tested condition are included in the opcode byte. the address of the byte to be tested follows immediately the opcode in the pro- gram space. the third byte is the jump displace- ment, which is in the range of -127 to +128. this displacement can be determined using a label, which is converted by the assembler. indirect . in the indirect addressing mode, the byte processed by the register-indirect instruction is at the address pointed by the content of one of the in- direct registers, x or y (80h,81h). the indirect reg- ister is selected by the bit 4 of the opcode. a regis- ter indirect instruction is one byte long. inherent . in the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. these instructions are one byte long.
58/84 st6365, st6375, st6385 ST6367, st6377, st6387 5.3 instruction set the st6 core offers a set of 40 basic instructions which, when combined with nine addressing modes, yield 244 usable opcodes. they can be di- vided into six different types: load/store, arithme- tic/logic, conditional branch, control instructions, jump/call, and bit manipulation. the following par- agraphs describe the different types. all the instructions belonging to a given type are presented in individual tables. load & store . these instructions use one, two or three bytes in relation with the addressing mode. one operand is the accumulator for load and the other operand is obtained from data memory using one of the addressing modes. for load immediate one operand can be any of the 256 data space bytes while the other is always immediate data. table 21. load & store instructions notes: x,y. indirect register pointers, v & w short direct registers # . immediate data (stored in rom memory) rr. data space register d . affected * . not affected instruction addressing mode bytes cycles flags zc ld a, x short direct 1 4 d * ld a, y short direct 1 4 d * ld a, v short direct 1 4 d * ld a, w short direct 1 4 d * ld x, a short direct 1 4 d * ld y, a short direct 1 4 d * ld v, a short direct 1 4 d * ld w, a short direct 1 4 d * ld a, rr direct 2 4 d * ld rr, a direct 2 4 d * ld a, (x) indirect 1 4 d * ld a, (y) indirect 1 4 d * ld (x), a indirect 1 4 d * ld (y), a indirect 1 4 d * ldi a, #n immediate 2 4 d * ldi rr, #n immediate 3 4 * *
59/84 st6365, st6375, st6385 ST6367, st6377, st6387 instruction set (contd) arithmetic and logic . these instructions are used to perform the arithmetic calculations and logic operations. in and, add, cp, sub instruc- tions one operand is always the accumulator while the other can be either a data space memory con- tent or an immediate value in relation with the ad- dressing mode. in clr, dec, inc instructions the operand can be any of the 256 data space ad- dresses. in com, rlc, sla the operand is always the accumulator. table 22. arithmetic & logic instructions notes: x,y.indirect register pointers, v & w short direct registersd. affected # . immediate data (stored in rom memory)* . not affected rr. data space register instruction addressing mode bytes cycles flags zc add a, (x) indirect 1 4 dd add a, (y) indirect 1 4 dd add a, rr direct 2 4 dd addi a, #n immediate 2 4 dd and a, (x) indirect 1 4 dd and a, (y) indirect 1 4 dd and a, rr direct 2 4 dd andi a, #n immediate 2 4 dd clr a short direct 2 4 dd clr r direct 3 4 * * com a inherent 1 4 dd cp a, (x) indirect 1 4 dd cp a, (y) indirect 1 4 dd cp a, rr direct 2 4 dd cpi a, #n immediate 2 4 dd dec x short direct 1 4 d * dec y short direct 1 4 d * dec v short direct 1 4 d * dec w short direct 1 4 d * dec a direct 2 4 d * dec rr direct 2 4 d * dec (x) indirect 1 4 d * dec (y) indirect 1 4 d * inc x short direct 1 4 d * inc y short direct 1 4 d * inc v short direct 1 4 d * inc w short direct 1 4 d * inc a direct 2 4 d * inc rr direct 2 4 d * inc (x) indirect 1 4 d * inc (y) indirect 1 4 d * rlc a inherent 1 4 dd sla a inherent 2 4 dd sub a, (x) indirect 1 4 dd sub a, (y) indirect 1 4 dd sub a, rr direct 2 4 dd subi a, #n immediate 2 4 dd
60/84 st6365, st6375, st6385 ST6367, st6377, st6387 instruction set (contd) conditional branch . the branch instructions achieve a branch in the program when the select- ed condition is met. bit manipulation instructions . these instruc- tions can handle any bit in data space memory. one group either sets or clears. the other group (see conditional branch) performs the bit test branch operations. control instructions . the control instructions control the mcu operations during program exe- cution. jump and call. these two instructions are used to perform long (12-bit) jumps or subroutines call inside the whole program space. table 23. conditional branch instructions notes : b. 3-bit address rr. data space register e. 5 bit signed displacement in the range -15 to +16 d . affected. the tested bit is shifted into carry. ee. 8 bit signed displacement in the range -126 to +129 * . not affected table 24. bit manipulation instructions notes: b. 3-bit address; * . not affected rr. data space register; table 25. control instructions notes: 1. this instruction is deactivatedand a wait is automatically executed instead of a stop if the watchdog function is selected . d . affected *. not affected table 26. jump & call instructions notes: abc. 12-bit address; * . not affected instruction branch if bytes cycles flags zc jrc e c = 1 1 2 * * jrnc e c = 0 1 2 * * jrz e z = 1 1 2 * * jrnz e z = 0 1 2 * * jrr b, rr, ee bit = 0 3 5 * d jrs b, rr, ee bit = 1 3 5 * d instruction addressing mode bytes cycles flags zc set b,rr bit direct 2 4 * * res b,rr bit direct 2 4 * * instruction addressing mode bytes cycles flags zc nop inherent 1 2 * * ret inherent 1 2 * * reti inherent 1 2 dd stop (1) inherent 1 2 * * wait inherent 1 2 * * instruction addressing mode bytes cycles flags zc call abc extended 2 4 * * jp abc extended 2 4 * *
61/84 st6365, st6375, st6385 ST6367, st6377, st6387 opcode map summary. the following table contains an opcode map for the instructions used by the st6 low 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 low hi hi 0 0000 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 ld 0 0000 e abc e b0,rr,ee e # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 1 0001 2 jrnz4 call2 jrnc5 jrs2 jrz4 inc2 jrc4 ldi 1 0001 e abc e b0,rr,ee e x e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm 2 0010 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 cp 2 0010 e abc e b4,rr,ee e # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 3 0011 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 ld 2 jrc 4 cpi 3 0011 e abc e b4,rr,ee e a,x e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm 4 0100 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 add 4 0100 e abc e b2,rr,ee e # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 5 0101 2 jrnz4 call2 jrnc5 jrs2 jrz4 inc2 jrc4 addi 5 0101 e abc e b2,rr,ee e y e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm 6 0110 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 inc 6 0110 e abc e b6,rr,ee e # e (x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 7 0111 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 ld 2 jrc 7 0111 e abc e b6,rr,ee e a,y e # 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 8 1000 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 ld 8 1000 e abc e b1,rr,ee e # e (x),a 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 9 1001 2 rnz 4 call 2 jrnc 5 jrs 2 jrz 4 inc 2 jrc 9 1001 e abc e b1,rr,ee e v e # 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc a 1010 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 and a 1010 e abc e b5,rr,ee e # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind b 1011 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 ld 2 jrc 4 andi b 1011 e abc e b5,rr,ee e a,v e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm c 1100 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 sub c 1100 e abc e b3,rr,ee e # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind d 1101 2 jrnz4 call2 jrnc5 jrs2 jrz4 inc2 jrc4 subi d 1101 e abc e b3,rr,ee e w e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm e 1110 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 dec e 1110 e abc e b7,rr,ee e # e (x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind f 1111 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 ld 2 jrc f 1111 e abc e b7,rr,ee e a,w e # 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc abbreviations for addressing modes: legend: dir direct # indicates illegal instructions sd short direct e 5 bit displacement imm immediate b 3 bit address inh inherent rr 1byte dataspace address ext extended nn 1 byte immediate data b.d bit direct abc 12 bit address bt bit test ee 8 bit displacement pcr program counter relative ind indirect 2 jrc e 1prc mnemonic addressing mode bytes cycle operand
62/84 st6365, st6375, st6385 ST6367, st6377, st6387 opcode map summary (continued) low 8 1000 9 1001 a 1010 b 1011 c 1100 d 1101 e 1110 f 1111 low hi hi 0 0000 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 4 ldi 2 jrc 4 ld 0 0000 e abc e b0,rr e rr,nn e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 3 imm 1 prc 1 ind 1 0001 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 dec 2 jrc 4 ld 1 0001 e abc e b0,rr e x e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir 2 0010 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 4 com 2 jrc 4 cp 2 0010 e abc e b4,rr e a e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 prc 1 ind 3 0011 2 jrnz4 jp2 jrnc4 set2 jrz4 ld2 jrc4 cp 3 0011 e abc e b4,rr e x,a e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir 4 0100 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 2 reti 2 jrc 4 add 4 0100 e abc e b2,rr e e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind 5 0101 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 dec 2 jrc 4 add 5 0101 e abc e b2,rr e y e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir 6 0110 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 2 stop 2 jrc 4 inc 6 0110 e abc e b6,rr e e (y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind 7 0111 2 jrnz4 jp2 jrnc4 set2 jrz4 ld2 jrc4 inc 7 0111 e abc e b6,rr e y,a e rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir 8 1000 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 2 jrc 4 ld 8 1000 e abc e b1,rr e # e (y),a 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 prc 1 ind 9 1001 2 rnz 4 jp 2 jrnc 4 set 2 jrz 4 dec 2 jrc 4 ld 9 1001 e abc e b1,rr e v e rr,a 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir a 1010 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 4 rcl 2 jrc 4 and a 1010 e abc e b5,rr e a e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind b 1011 2 jrnz4 jp2 jrnc4 set2 jrz4 ld2 jrc4 and b 1011 e abc e b5,rr e v,a e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir c 1100 2 jrnz4 jp2 jrnc4 res2 jrz2 ret2 jrc4 sub c 1100 e abc e b3,rr e e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind d 1101 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 dec 2 jrc 4 sub d 1101 e abc e b3,rr e w e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir e 1110 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 2 wait 2 jrc 4 dec e 1110 e abc e b7,rr e e (y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind f 1111 2 jrnz4 jp2 jrnc4 set2 jrz4 ld2 jrc4 dec f 1111 e abc e b7,rr e w,a e rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir abbreviations for addressing modes: legend: dir direct # indicates illegal instructions sd short direct e 5 bit displacement imm immediate b 3 bit address inh inherent rr 1byte dataspace address ext extended nn 1 byte immediate data b.d bit direct abc 12 bit address bt bit test ee 8 bit displacement pcr program counter relative ind indirect 2 jrc e 1prc mnemonic addressing mode bytes cycle operand
63/84 st6365, st6375, st6385 ST6367, st6377, st6387 6 electrical characteristics 6.1 absolute maximum ratings this product contains devices to protect the inputs against damage due to high static voltages, how- ever it is advised to take normal precaution to avoid application of any voltage higher than maxi- mum rated voltages. for proper operation it is recommended that vi and vo must be higher than v ss and smaller than v dd . reliability is enhanced if unused inputs are connected to an appropriated logic voltage level (v dd or v ss ). power considerations .the average chip-junc- tion temperature, tj, in celsius can be obtained from: tj= ta + pd x rthja where: ta = ambient temperature. rthja =package thermal resistance (junction-to ambient). pd = pint + pport. pint = idd x v dd (chip internal pow- er). pport = port power dissipation (determined by the user). note : stresses above those listed as absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended p eriods may affect device reliability. thermal characteristics 6.2 recommended operating conditions eeprom information the st63xx eeprom single poly process has been specially developed to achieve 300.000 write/erase cycles and a 10 years data retention. symbol parameter value unit v dd supply voltage -0.3 to 7.0 v v i input voltage (afc in) v ss - 0.3 to +13 v v i input voltage (other inputs) v ss - 0.3 to v dd + 0.3 v v o output voltage (pa4-pa7, pc4-pc7, da0-da5) v ss - 0.3 to +13 v v o output voltage (other outputs) v ss - 0.3 to v dd + 0.3 v i o current drain per pin excluding v dd , v ss , pa6, pa7 + 10 ma i o current drain per pin (pa6-pa7) + 50 ma iv dd total current into v dd (source) 50 ma iv ss total current out of v ss (sink) 150 ma t j junction temperature 150 c t stg storage temperature -60 to 150 c symbol parameter test conditions value unit min. typ. max. rthja thermal resistance psdip42 67 c/w symbol parameter test conditions value unit min. typ. max. t a operating temperature 1 suffix versions 0 70 c v dd operating supply voltage 4.5 5.0 6.0 v f osc oscillator frequency run & wait modes 8 8.1 mhz f osdosc on-screen display oscillator frequency 8.0 mhz
64/84 st6365, st6375, st6385 ST6367, st6377, st6387 6.3 dc electrical characteristics (ta = 0 to +70c unless otherwise specified). table 27: dc electrical characteristics symbol parameter test conditions value unit min. typ. max. v il input low level voltage all i/o pins 0.2xv dd v v ih input high level voltage all i/o pins 0.8xv dd v v hys hysteresis voltage (1) all i/o pins v dd = 5v 1.0 v v ol low level output voltage da0-da5, pb0-pb6, osd outputs, pc0-pc7, o0, o1, pa0-pa5 v dd = 4.5v i ol = 1.6ma i ol = 5.0ma 0.4 1.0 v v v ol low level output voltage pa6-pa7 v dd = 4.5v i ol = 1.6ma i ol = 25ma 0.4 1.0 v v v ol low level output voltage osdoscout oscout v dd = 4.5v i ol = 0.4ma 0.4 v v ol low level output voltage vs output v dd = 4.5v i ol = 0.5ma i ol = 1.6ma 0.4 1.0 v v v oh high level output voltage pb0-pb7, pa0-pa3, osd outputs v dd = 4.5v i oh = C 1.6ma 4.1 v v oh high level output voltage osdoscout, oscout, v dd = 4.5v i oh = C 0.4ma 4.1 v v oh high level output voltage vs output v dd = 4.5v i oh = - 0.5ma 4.1 v i pu input pull up current input mode with pull-up pb0-pb6, pa0-pa3, pc0-pc3, v in = v ss C 100 C 50 C 25 a i pu input pull up current oscin v in = v ss C 50 C 25 C 10 a i il i ih input leakage current oscin v in = v ss v in = v dd C 10 0.1 C 1 1 C 0.1 10 m a i il input pull-down current in reset oscin 100 m a i il i ih input leakage current all i/o input mode no pull-up osdoscin v in = v dd or v ss -10 10 m a v dd ram ram retention voltage in reset mode 1.5 v i il i ih input leakage current reset pin with pull-up v in = v ss C 50 C 30 C 10 m a
65/84 st6365, st6375, st6385 ST6367, st6377, st6387 note 1. not 100% tested i il i ih input leakage current afc pin v ih = v dd v il = v ss v ih = 12.0v -1 1 40 m a i oh output leakage current da0-da5, pa4-pa5, pc0-pc7, o0, o1 v oh = v dd 10 m a i oh output leakage current high volt- age da0-da5, pa4-pa7, pc4-pc7, o0, o1 v oh = 12v 40 m a i dd supply current run mode f osc = 8mhz, iload= 0ma v dd = 6.0v 616ma i dd supply current wait mode f osc = 8mhz, iload= 0ma v dd = 6v 310ma i dd supply current at transition to reset f osc = not app, iload= 0ma v dd = 6v 0.1 1 ma v on reset trigger level on reset pin 0.3xv dd v v off reset trigger level off reset pin 0.8xv dd v v ta input level absolute tolerance a/d afc pin v dd = 5v 200 mv v tr input level relatice tolerance (1) a/d afc pin relative to other levels v dd = 5v 100 mv table 27: dc electrical characteristics symbol parameter test conditions value unit min. typ. max.
66/84 st6365, st6375, st6385 ST6367, st6377, st6387 6.4 ac electrical characteristics (ta = 0 to +70c, f osc =8mhz, v dd =4.5 to 6.0v unless otherwise specified) notes: 1. a clock other than 8mhz will affect the frequency response of those peripherals (d/a, and spis) whose clock is derived from t he system clock. 2. the rise and fall times of port a have been increased in order to avoid current spikes while maintaining a high drive capabi lity 3. not 100% tested 4. based on extrapolated data symbol parameter test conditions value unit min. typ. max. t wres minimum pulse width reset pin 125 ns t ohl high to low transition time pa6, pa7 v dd = 5v, cl = 100pf (2) 100 ns t ohl high to low transition time da0-da5, pb0-pb6, osd outputs, pc0-pc7 v dd = 5v, cl = 100pf 20 ns t olh low to high transition time pb0-pb6, pa0-pa3, osd outputs, pc0-pc3 v dd = 5v, cl = 100pf 20 ns f da d/a converter repetition fre- quency (1) 31.25 khz f sio sio baudrate (1) 62.50 khz t wee eeprom write time t a = 25c one byte 5 10 ms endurance eeprom write/erase cy- cles q a l ot acceptance criteria 300,000 > 1 million cycles retention eeprom data retention (4) t a = 25c 10 years c in input capacitance (3) all inputs pins 10 pf c out output capacitance (3) all outputs pins 10 pf coscin, coscout oscillator pins internal capacitance (3) 5pf cosdin, cosdout oscillator pins external capacitance (3) recommended 15 25 pf
67/84 st6365, st6375, st6385 ST6367, st6377, st6387 7 general information 7.1 package mechanical data figure 33. 42-pin plastic shrink dual-in-line package 7.2 ordering information the following chapter deals with the procedure for transfer the program/data rom codes to sgs- thomson. communication of the rom codes . to commu- nicate the contents of program/data rom memo- ries to sgs-thomson, the customer must send: C one file in intel intellec 8/mds format for the program memory; C one file in intel intellec 8/mds format for the eeprom initial content (this file is optional). C two files in intel...format for the osd font memory C the option list described below. the program rom should respect the rom mem- ory map as in table 4 . the rom code must be generated with an st6 assembler. before programming the eprom, the eprom programmer buffer must be filled with ffh. dim. mm inches min typ max min typ max a 5.08 0.200 a1 0.51 0.020 a2 3.05 3.81 4.57 0.120 0.150 0.180 b 0.46 0.56 0.018 0.022 b2 1.02 1.14 0.040 0.045 c 0.23 0.25 0.38 0.009 0.010 0.015 d 36.58 36.83 37.08 1.440 1.450 1.460 e 15.24 16.00 0.600 0.630 e1 12.70 13.72 14.48 0.500 0.540 0.570 e 1.78 0.070 ea 15.24 0.600 eb 18.54 0.730 ec 1.52 0.000 0.060 l 2.54 3.30 3.56 0.100 0.130 0.140 number of pins n42 e1 ec ea eb .015 gage plane lead detail e eb c e d b b2 a2 a1 e a l vr01725g
68/84 st6365, st6375, st6385 ST6367, st6377, st6387 general information (contd) 7.3 customer eeprom initial contents: a. the content should be written into an intel intellec format file. b in the case of 384 bytes of eeprom, the start- ing address is 000h and the end address is 17fh. the order of the pages (64 bytes each) is an in the specification (i.e. b7, b1 b0: 001, 010, 011, 101, 110. 111). c. undefined or don't care bytes should have the content ffh. 7.4 osd test character in order to allow the testing of the on-chip osd macrocell the following character must be provided at the fixed 3fh (63) position of the second osd bank. listing generation & verification. when sgs-thomson receives the files, a computer listing is generated from them. this listing refers extractly to the mask that will be used to produce the microcontroller. then the listing is returned to the customer that must thoroughly check, com- plete, sign and return it to sgs-thomson. the signed list constitutes a part of the contractual agreement for the creation of the customer mask. sgs-thomson sales organization will provide detailed information on contractual points. figure 34. osd test character 7.5 ordering information table note : xxx is the rom code identifier that is allocated by sgs- thomson after receipt of all required options and the related rom file. sales type rom/ eeprom size d/ a converter temperature range package st6365b1/ xxx 8k/ 384 bytes 4 0 to + 70 c psdip42 ST6367b1/ xxx 8k/ 384 bytes 6 0 to + 70 c psdip42 st6375b1/ xxx 14k/ 384 bytes 4 0 to + 70 c psdip42 st6377b1/ xxx 14k/ 384 bytes 6 0 to + 70 c psdip42 st6385b1/ xxx 20k/ 384 bytes 4 0 to + 70 c psdip42 st6387b1/ xxx 20k/ 384 bytes 6 0 to + 70 c psdip42
69/84 st6365, st6375, st6385 ST6367, st6377, st6387 st636x, 7x, 8x rom microcontroller option list customer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone no . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . st638x series device [ ] (d) package [ ] (p) temperature range [ ] (t) sales type marking [ ] (y/n) special marking [ ] (y/n) line 1 .............. (n) line 2 .............. (n) line 3 .............. (n) traceability marking (mandatory) (d) 1 = st6365, 2 = ST6367, 3 = st6375, 4 = st6377, 5 = st6385, 6= st6387 8 = st6368, 9 = st6378 (p) b = dual in line plastic (t) 1 = 0 to +70 c 4 = -10 to +70 c (n) letters, digits, ., -, / and spaces only st638x option list osd polarity options (put a cross on selected item) : positive negative vsync, hsync [ ] [ ] r,g,b [ ] [ ] blank [ ] [ ] st638x check list yes no rom code [ ] [ ] osd code: odd & even [ ] [ ] for st6365/67/75/77/85/87 osd code: [ ] [ ] for st6368/78 eeprom code (if desired) [ ] [ ] notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . date . . . . . . . . . . . . . . . . . . . . .
70/84 st6365, st6375, st6385 ST6367, st6377, st6387 notes:
december 1997 71/84 this is preliminary information on a new product in development or undergoing evaluation. details are subject to change without notice. r rev. 2.2 st63e85, t85 st63e87, t87 8-bit eprom/otp mcus with on-screen-display for tv tuning n 4.5 to 6v supply operating range n 8mhz maximum clock frequency n user program rom: up to 20140 bytes n reserved test rom: up to 340 bytes n data rom: user selectable size n data ram: 256 bytes n data eeprom: 384 bytes n 42-pin shrink dual in line plastic package for otp versions n 42-pin shrink dual in line ceramic package for eprom versions n up to 22 software programmable general purpose inputs/outputs, including 2 direct led driving outputs n two timers each including an 8-bit counter with a 7-bit programmable prescaler n digital watchdog function n serial peripheral interface (spi) supporting s- bus/ i 2 c bus and standard serial protocols n spi for external frequency synthesis tuning n 14 bit counter for voltage synthesis tuning n up to six 6-bit pwm d/a converters n afc a/d converter with 0.5v resolution n five interrupt vectors (irin/nmi, timer 1 & 2, vsync, pwr int.) n on-chip clock oscillator n 5 lines by 15 characters on-screen display generator with 128 characters n all rom types are supported by pin-to-pin eprom and otp versions. n the development tool of the st6365, st6375, st6385, ST6367, st6377, st6387 microcon- trollers consists of the st638x-emu2 emula- tion and development system to be connected via a standard rs232 serial line to an ms-dos personal computer. device summary eprom device otp device rom (bytes) d/a converter st63e85 st63t85 20k 4 st63e87 st63t87 20k 6 psdip42 (refer to end of document for ordering information) csdip42
72/84 st63e85, t85 st63e87, t87 1 general description 1.1 introduction the st63e8x microcontrollers are members of the 8-bit hcmos st638x family, a series of devices specially oriented to tv applications. different rom size and peripheral configurations are avail- able to give the maximum application and cost flexibility. they are the eprom/otp versions of the st636x, 7x, 8x, rom devices and are suitable for product prototyping and low volume produc- tion. all st638x members are based on a building block approach: a common core is surrounded by a combination of on-chip peripherals (macrocells) available from a standard library. these peripher- als are designed with the same core technology providing full compatibility and short design time. many of these macrocells are specially dedicated to tv applications. the macrocells of the st638x family are: two timer peripherals each including an 8-bit counter with a 7-bit software programma- ble prescaler (timer), a digital hardware activated watchdog function (dhwd), a 14-bit voltage syn- thesis tuning peripheral, a serial peripheral inter- face (spi), up to six 6-bit pwm d/a converters, an afc a/d converter with 0.5v resolution, an on- screen display (osd) with 15 characters per line and 128 characters (in two banks each of 64 char- acters). in addition the following memory resourc- es are available: program eprom (up to 20k), data ram (256 bytes), eeprom (384 bytes). re- fer to pin configurations figures and to st638x de- vice summary ( table 1 ) for the definition of st638x family members and a summary of differ- ences among the different types. table 1. device summary device eprom (bytes) otp (bytes) ram (bytes) eeprom (bytes) afc vs d/a colour pins target r0m devices st63e85 20k 256 384 yes yes 4 3 st6365, 75, 85 st63t85 20k 256 384 yes yes 4 3 st6365, 75, 85 st63e87 20k 256 384 yes yes 6 3 ST6367, 77 87 st63t87 20k 256 384 yes yes 6 3 ST6367, 77 87
73/84 st63e85, t85 st63e87, t87 figure 1. block diagram test irin/pc6 interrupt up to 20kbytes pc stack level 1 stack level 2 stack level 3 stack level 4 stack level 5 stack level 6 power supply oscillator reset data rom user selectable data ram 256 bytes port a port b port c 8 bit core test timer 1 pa0 - pa7* v dd v ss oscin oscout reset user program memory timer 2 inputs data eeprom 384 bytes pc2, pc4 - pc7* d/a outputs afc & vs* r, g, b, blank vs output & on-screen digital watchdog da0 - da5 *refer to pin description for additional information serial peripheral pc0/scl pc1/sda pc3/sen timer afc outputs display interface hsync, vsync vr01753 osdoscout osdoscin pb0 - pb2, pb4 pb6*
74/84 st63e85, t85 st63e87, t87 1.2 pin description v dd and v ss . power is supplied to the mcu using these two pins. v dd is power and v ss is the ground connection. oscin, oscout. these pins are internally con- nected to the on-chip oscillator circuit. a quartz crystal or a ceramic resonator can be connected between these two pins in order to allow the cor- rect operation of the mcu with various stability/ cost trade-offs. the oscin pin is the input pin, the oscout pin is the output pin. reset . the active low reset pin is used to start the microcontroller to the beginning of its program. additionally the quartz crystal oscillator will be dis- abled when the reset pin is low to reduce power consumption during reset phase. test/v pp . the test pin must be held at v ss for normal operation. if this pin is connected to a +12.5v level during the reset phase, the eprom programming mode is entered. pa0-pa7 . these 8 lines are organized as one i/o port (a). each line may be configured as either an input with or without pull-up resistor or as an out- put under software control of the data direction register. pins pa4 to pa7 are configured as open- drain outputs (12v drive). on pa4-pa7 pins the in- put pull-up option is not available while pa6 and pa7 have additional current driving capability (25ma, vol:1v). pa0 to pa3 pins are configured as push-pull. pb0-pb2, pb4-pb6 . these 6 lines are organized as one i/o port (b). each line may be configured as either an input with or without internal pull-up resistor or as an output under software control of the data direction register. pc0-pc7 . these 8 lines are organized as one i/o port (c). each line may be configured as either an input with or without internal pull-up resistor or as an output under software control of the data direc- tion register. pins pc0 to pc3 are configured as open-drain (5v drive) in output mode while pc4 to pc7 are open-drain with 12v drive and the input pull-up options does not exist on these four pins. pc0, pc1 and pc3 lines when in output mode are anded with the spi control signals and are all open-drain. pc0 is connected to the spi clock sig- nal (scl), pc1 with the spi data signal (sda) while pc3 is connected with spi enable signal (sen, used in s-bus protocol). pin pc4 and pc6 can also be inputs to software programmable edge sensitive latches which can generate interrupts; pc4 can be connected to power interrupt while pc6 can be connected to the irin/nmi interrupt line. da0-da5 . these pins are the six pwm d/a out- puts of the 6-bit on-chip d/a converters. these lines have open-drain outputs with 12v drive. the output repetition rate is 31.25khz (with 8mhz clock). afc . this is the input of the on-chip 10 levels comparator that can be used to implement the afc function. this pin is an high impedance input able to withstand signals with a peak amplitude up to 12v. osdoscin, osdoscout . these are the on screen display oscillator terminals. an oscillation capacitor and coil network have to be connected to provide the right signal to the osd. hsync, vsync . these are the horizontal and vertical synchronization pins. the active polarity of these pins to the osd macrocell can be selected by the user as rom mask option. if the device is specified to have negative logic inputs, then these signals are low the osd oscillator stops. if the de- vice is specified to have positive logic inputs, then when these signals are high the osd oscillator stops. vsync is also con-nected to the vsync interrupt. r, g, b, blank . outputs from the osd. r, g and b are the color outputs while blank is the blank- ing output. all outputs are push-pull. the active polarity of these pins can be selected by the user as rom mask option. vs . this is the output pin of the on-chip 14-bit volt- age synthesis tuning cell (vs). the tuning signal present at this pin gives an approximate resolution of 40khz per step over the uhf band. this line is a push-pull output with standard drive.
75/84 st63e85, t85 st63e87, t87 figure 2. st63e65, t85 pin configuration figure 3. st63e87, t87pin configuration table 2. pin summary 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 vs da1 da2 da3 da4 pb0 pb1 pb2 afc pb4 pb5 pb6 pa0 pa1 pa2 pa3 pa4 pa5 pa6 (hd0) pa7 (hd1) v ss v dd pc0/scl pc1/sda pc2 pc3/sen pc4/pwrin pc5 pc7 oscin oscout test/v pp (1) vsync blank b g r pc6/irin (1) this pin is also the v pp input for otp/eprom devices reset hsync osdoscin osdoscout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 da0 da1 da2 da3 da4 da5 pb1 pb2 afc pb4 pb5 pb6 pa0 pa1 pa2 pa3 pa4 pa5 pa6 (hd0) pa7 (hd1) v ss v dd pc0/scl pc1/sda pc2 pc3/sen pc4/pwrin pc5 vs oscin oscout test/v pp (1) vsync blank b g r pc6/irin (1) this pin is also the v pp input for otp/eprom devices reset hsync osdoscin osdoscout pin function description da0 to da5 output, open- drain, 12v afc input, high impedance, 12v vs output, push- pull r, g, b, blank output, push- pull hsync, vsync input, pull- up, schmitt trigger osdoscin input, high impedance osdoscout output, push- pull test /v pp input, pull- down oscin input, resistive bias, schmitt trigger to reset logic only oscout output, push- pull reset input, pull- up, schmitt trigger input pa0- pa3 i/ o, push- pull, software input pull- up, schmitt trigger input pa4- pa5 i/ o, open- drain, 12v, no input pull- up, schmitt trigger input pa6- pa7 i/ o, open- drain, 12v, no input pull- up, schmitt trigger input, high drive pb0- pb2 i/ o, push- pull, software input pull- up, schmitt trigger input pb4- pb6 i/ o, push- pull, software input pull- up, schmitt trigger input pc0- pc3 i/ o, open- drain, 5v, software input pull- up, schmitt trigger input pc4- pc7 i/ o, open- drain, 12v, no input pull- up, schmitt trigger input v dd , v ss power supply pins
76/84 st63e85, t85 st63e87, t87 1.3 eprom/otp description the st63e8x is the eprom version of the st636x, 7x, 8x rom products. they are intended for use during the development of an application, and for pre-production and small volume produc- tion. the st63t8x otp have the same character- istics. they both include eprom memory instead of the rom memory of the st638x, and so the program and constants of the program can be eas- ily modified by the user with the st63e8x eprom programming board from sgs-thomson. the rom mask options of the st638x for osd polarities (hsync, vsync, r, g, b, blank) are emulated with an eprom option byte. this is programmed by the eprom programming board and its associated software. the eprom option byte content will define the osd options as follows: b7-3: device specific bits, these reserved bits must be programmed with 00010. opt 0: this bit defines the osd h/vsync polarity, if 0 the polarity will be negative if 1 the polarity will be positive. opt 1: this bit defines the rgb polarity, if 0 the po- larity will be negative if 1 the polarity will be positive. opt 2: this bit defines the blank polarity, if 0 the polarity will be negative if 1 the polarity will be pos- itive. from a user point of view (with the following ex- ceptions) the st63e8x,t8x products have exactly the same software and hardware features of the rom version. an additional mode is used to con- figure the part for programming of the eprom, this is set by a +12.5v voltage applied to the test/vpp pin. the programming of the st63e8x,t8x is described in the user manual of the eprom programming board. on the st63e8x, all the 20140 bytes of pro- gram memory are available for the user, as all the eprom memory can be erased by exposure to uv light. on the st63t8x (otp device) a re- served area for test purposes exists, as for the st638x rom device. in order to avoid any dis- crepancy between program functionality when us- ing the eprom, otp and rom it is recommend- ed not to use these reserved areas, even when using the st63e8x. the table 4 on page 10 is a summary of the eprom/rom map and its reserved area. 1.4 power on reset this feature is not available on the st63e8x, t8x. it is recommended to use the following application schematics: figure 4. reset network this application schematics can also be used for the rom devices. the reader is asked to refer to the datasheet of the st636x, 7x, 8x rom- based device for further details. 1.5 eprom erasing the eprom of the windowed package of the st63e8x may be erased by exposure to ultra vio- let light. the erasure characteristic of the st63e8x eprom is such that erasure begins when the memory is exposed to light with wave lengths shorter than approximately 4000?. it should be noted that sunlight and some types of fluorescent lamps have wavelengths in the range 3000- 4000?. it is thus recommended that the window of the st63e8x package be covered by an opaque label to prevent unintentional erasure problems when testing the application in such an environ- ment.the recommended erasure procedure of the st63e8x eprom is exposure to short wave ultra- violet light which has wavelength 2537?. the inte- grated dose (i.e. uv intensity x exposure time) for erasure should be a minimum of 15 w-sec/cm2. the erasure time with this dosage is approximate- ly 15 to 20 minutes using an ultraviolet lamp with 12000mw/cm2 power rating. the st63e8x should be placed within 2.5cm (1 inch) of the lamp tubes during erasure. 70 00010opt 2opt 1opt 0 reset pin vdd
77/84 st63e85, t85 st63e87, t87 2 electrical characteristics 2.1 absolute maximum ratings this product contains devices to protect the inputs against damage due to high static voltages, how- ever it is advised to take normal precaution to avoid application of any voltage higher than maxi- mum rated voltages. for proper operation it is recommended that vi and vo must be higher than v ss and smaller than v dd . reliability is enhanced if unused inputs are connected to an appropriated logic voltage level (v dd or v ss ). power considerations .the average chip-junc- tion temperature, tj, in celsius can be obtained from: tj= ta + pd x rthja where:ta = ambient temperature. rthja = package thermal resistance (junction-to ambient). pd = pint + pport. pint = idd x v dd (chip internal pow- er). pport = port power dissipation (determined by the user). thermal characteristics 2.2 recommended operating conditions eeprom information the st63xx eeprom single poly process has been specially developed to achieve 300.000 write/erase cycles and a 10 years data retention. symbol parameter value unit v dd supply voltage -0.3 to 7.0 v v i input voltage (afc in) v ss - 0.3 to +13 v v i input voltage (other inputs) v ss - 0.3 to v dd + 0.3 v v o output voltage (pa4-pa7, pc4-pc7, da0-da5) v ss - 0.3 to +13 v v o output voltage (other outputs) v ss - 0.3 to v dd + 0.3 v v pp eprom programming voltage - 0.3 to 13.0 v i o current drain per pin excluding v dd , v ss , pa6, pa7 + 10 ma i o current drain per pin (pa6, pa7) + 50 ma iv dd total current into v dd (source) 50 ma iv ss total current out of v ss (sink) 150 ma t j junction temperature 150 c symbol parameter test conditions value unit min. typ. max. rthja thermal resistance psdip42 67 c/w symbol parameter test conditions value unit min. typ. max. t a operating temperature 0 70 c v dd operating supply voltage 4.5 5.0 6.0 v v pp eprom programming voltage 12.0 12.5 13.0 v f osc oscillator frequency run & wait modes 8.0 8.1 mhz f osdosc on-screen display oscillator frequency 8.0 mhz
78/84 st63e85, t85 st63e87, t87 2.3 dc electrical characteristics (ta = 0 to +70c unless otherwise specified). table 3: dc electrical characteristics symbol parameter test conditions value unit min. typ. max. v il input low level voltage all i/o pins 0.2xv dd v v ih input high level voltage all i/o pins 0.8xv dd v v hys hysteresis voltage (1) all i/o pins v dd = 5v 1.0 v v ol low level output voltage da0-da5, pb0-pb6, osd outputs, pc0-pc7, o0, o1, pa0-pa5 v dd = 4.5v i ol = 1.6ma i ol = 5.0ma 0.4 1.0 v v v ol low level output voltage pa6-pa7 v dd = 4.5v i ol = 1.6ma i ol = 25ma 0.4 1.0 v v v ol low level output voltage osdoscout oscout v dd = 4.5v i ol = 0.4ma 0.4 v v ol low level output voltage vs output v dd = 4.5v i ol = 0.5ma i ol = 1.6ma 0.4 1.0 v v v oh high level output voltage pb0-pb7, pa0-pa3, osd outputs v dd = 4.5v i oh = C 1.6ma 4.1 v v oh high level output voltage osdoscout, oscout, v dd = 4.5v i oh = C 0.4ma 4.1 v v oh high level output voltage vs output v dd = 4.5v i oh = - 0.5ma 4.1 v i pu input pull up current input mode with pull-up pb0-pb6, pa0-pa3, pc0-pc3, v in = v ss C 100 C 50 C 25 ma i il i ih input leakage current oscin v in = v ss v in = v dd C 10 0.1 C 1 1 C 0.1 10 m a m a i il input pull-down current in reset oscin 100 m a i il i ih input leakage current all i/o input mode no pull-up osdoscin v in = v dd or v ss -10 10 m a v dd ram ram retention voltage in reset 1.5 v i il i ih input leakage current reset pin with pull-up v in = v ss C 50 C 30 C 10 m a
79/84 st63e85, t85 st63e87, t87 note 1. not 100% tested i il i ih input leakage current afc pin v ih = v dd v il = v ss v ih = 12.0v -1 1 40 m a i oh output leakage current da0-da5, pa4-pa5, pc0-pc7, o0, o1 v oh = v dd 10 m a i oh output leakage current high volt- age da0-da5, pa4-pa7, pc4-pc7, o0, o1 v oh = 12v 40 m a i dd supply current run mode f osc = 8mhz, iload= 0ma v dd = 6.0v 616ma i dd supply current wait mode f osc = 8mhz, iload= 0ma v dd = 6v 310ma i dd supply current at transition to re- set f osc = not app, iload= 0ma v dd = 6v 0.1 1 ma v on reset trigger level on reset pin 0.3xv dd v v off reset trigger level off reset pin 0.8xv dd v v ta input level absolute tolerance a/d afc pin v dd = 5v 200 mv v tr input level relatice tolerance (1) a/d afc pin relative to other levels v dd = 5v 100 mv table 3: dc electrical characteristics symbol parameter test conditions value unit min. typ. max.
80/84 st63e85, t85 st63e87, t87 2.4 ac electrical characteristics (ta = 0 to +70c, f osc =8mhz, v dd =4.5 to 6.0v unless otherwise specified) notes: 1. a clock other than 8mhz will affect the frequency response of those peripherals (d/a, and spis) whose clock is derived from t he system clock. 2. the rise and fall times of port a have been increased in order to avoid current spikes while maintaining a high drive capabi lity 3. not 100% tested 4. based on extrapolated data symbol parameter test conditions value unit min. typ. max. t wres minimum pulse width reset pin 125 ns t ohl high to low transition time pa6, pa7 v dd = 5v, cl = 1000pf (2) 100 ns t ohl high to low transition time da0-da5, pb0-pb6, osd outputs, pc0-pc7 v dd = 5v, cl = 100pf (2) 20 ns t olh low to high transition time pb0-pb6, pa0-pa3, osd outputs, pc0-pc3 v dd = 5v, cl = 100pf 20 ns t oh data hold time spi after clock goes low i2cbus/s-bus only pb0-pb6, pa0-pa3, osd outputs, pc0-pc3 v dd = 5v, cl = 100pf 175 ns f da d/a converter repetition fre- quency (1) 31.25 khz f sio sio baudrate (1) 62.50 khz t wee eeprom write time t a = 25c one byte 5 10 ms endurance eeprom write/erase cy- cles q a l ot acceptance criteria 300,000 > 1 million cycles retention eeprom data retention (4) t a = 25c 10 years c in input capacitance (3) all inputs pins 10 pf c out output capacitance (3) all outputs pins 10 pf coscin, coscout oscillator pins internal capacitance (3) 5pf cosdin, cosdout oscillator pins external capacitance 15 25 pf
81/84 st63e85, t85 st63e87, t87 3 general information 3.1 ordering information the following chapter deals with the procedure for transfer the program/data rom codes to sgs- thomson. communication of the rom codes . to commu- nicate the contents of program/data rom memo- ries to sgs-thomson, the customer must send: C one file in intel intellec 8/mds format (either as an eprom or as a ms-dos diskette) for the program memory; C one file in intel intellec 8/mds format (either as an eprom or as a ms-dos diskette) for the eeprom initial content (this file is option- al). the program rom should respect the rom mem- ory map as in table 4 . the rom code must be generated with an st6 assembler. before programming the eprom, the eprom programmer buffer must be filled with ffh. for shipment to sgs-thomson, the master eproms should be placed in a conductive ic car- rier and packed carefully. 3.2 customer eeprom initial contents: format a. the content should be written into an intel intellec format file. b in the case of 384 bytes of eeprom, the start- ing address is 000h and the end address is 7fh. the order of the pages (64 bytes each) is an in the specification (i.e. b7, b1 b0: 001, 010, 011, 101, 110. 111). c. undefined or don't care bytes should have the content ffh. 3.3 osd test character in order to allow the testing of the on-chip osd macrocell the following character must be provided at the fixed 3fh (63) position of the second osd bank. listing generation & verification. when sgs-thomson receives the files, a computer listing is generated from them. this listing refers extractly to the mask that will be used to produce the microcontroller. then the listing is returned to the customer that must thoroughly check, com- plete, sign and return it to sgs-thomson. the signed list constitutes a part of the contractual agreement for the creation of the customer mask. sgs-thomson sales organization will provide detailed information on contractual points. figure 5. osd test character
82/84 st63e85, t85 st63e87, t87 3.4 package mechanical data figure 6. 42-pin plastic shrink dual-in-line package figure 7. 42-pin ceramic shrink dual-in-line package dim. mm inches min typ max min typ max a 5.08 0.200 a1 0.51 0.020 a2 3.05 3.81 4.57 0.120 0.150 0.180 b 0.46 0.56 0.018 0.022 b2 1.02 1.14 0.040 0.045 c 0.23 0.25 0.38 0.009 0.010 0.015 d 36.58 36.83 37.08 1.440 1.450 1.460 e 15.24 16.00 0.600 0.630 e1 12.70 13.72 14.48 0.500 0.540 0.570 e 1.78 0.070 ea 15.24 0.600 eb 18.54 0.730 ec 1.52 0.000 0.060 l 2.54 3.30 3.56 0.100 0.130 0.140 number of pins n42 e1 ec ea eb .015 gage plane lead detail e eb c e d b b2 a2 a1 e a l vr01725g dim. mm inches min typ max min typ max a 4.01 0.158 a1 0.76 0.030 b 0.38 0.46 0.56 0.015 0.018 0.022 b1 0.76 0.89 1.02 0.030 0.035 0.040 c 0.23 0.25 0.38 0.009 0.010 0.015 d 36.68 37.34 38.00 1.444 1.470 1.496 d1 35.56 1.400 e1 14.48 14.99 15.49 0.570 0.590 0.610 e 1.78 0.070 g 12.70 12.95 13.21 0.500 0.510 0.520 g1 12.70 12.95 13.21 0.500 0.510 0.520 g2 1.14 0.045 l 2.92 5.08 0.115 0.200 s 0.89 0.035 ? 0.350 number of pins n42 cdip42so
83/84 st63e85, t85 st63e87, t87 st63e8x, t8x microcontroller option list customer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone no . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . st63t8x series device [ ] (d) package [ ] (p) temperature range [ ] (t) sales type marking [ ] (y/n) special marking [ ] (y/n) line 1 ".............." (n) line 2 ".............." (n) line 3 ".............." (n) traceability marking (mandatory) (d) 1 = st63t85, 2 = st63t87, 3 = st63t78 (p) b = dual in line plastic (t) 1 = 0 to +70 c (n) letters, digits, '.', '-', '/' and spaces only st63t8x check list yes no osd code: odd & even [ ] [ ] for st63t85/t87 osd code: [ ] [ ] for st63t78 notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . date . . . . . . . . . . . . . . . . . . . . .
84/84 st63e85, t85 st63e87, t87 3.5 ordering information table information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of sgs-thomson microelectronics. ? 1997 sgs-thomson microelectronics - all rights reserved. purchase of i 2 c components by sgs-thomson microelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. sales type eprom/ eeprom size d/ a converter temperature range package st63e85d1/ xx 20k/ 384 bytes 4 0 to + 70 c csdip42w st63e87d1/ xx 20k/ 384 bytes 6 0 to + 70 c csdip42w st63t85b1/ xx 20k/ 384 bytes 4 0 to + 70 c psdip42 st63t87b1/ xx 20k/ 384 bytes 6 0 to + 70 c psdip42

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